Reputation: 15
I've written down this following "Design source" code (on Xilinx Vivado) The code is written in System Verilog, and it is the Hamming 7,4 encoder
https://en.wikipedia.org/wiki/Hamming(7,4)
module eccproj(
input logic [3:0] data_in,
output logic [6:0] hamcode);
logic p1,p2,p4;
always @(*) begin
p1 = data_in[0] + data_in[1] + data_in[3];
p2 = data_in[0] + data_in[2] + data_in[3];
p4 = data_in[1] + data_in[2] + data_in[3];
// Input : d3 d2 d1 d0
//Output : d7 d6 d5 p4 d3 d2 d1
assign hamcode = {data_in[3:1] , p4 , data_in[0] , p2 , p1}; // Error on this line
end
endmodule
I am getting error in the line with the comment, and the error reads as follows :
[Synth 8-27] procedural assign not supported
I know that, in Verilog the above assignment works, but how to work it using System Verilog.
It would be great if someone could suggest a way to get rid of the error.
Upvotes: 1
Views: 759
Reputation: 42673
You do not need the assign
keyword inside a combinational block
module eccproj(
input logic [3:0] data_in,
output logic [6:0] hamcode);
logic p1,p2,p4;
always_comb begin
p1 = data_in[0] + data_in[1] + data_in[3];
p2 = data_in[0] + data_in[2] + data_in[3];
p4 = data_in[1] + data_in[2] + data_in[3];
// Input : d3 d2 d1 d0
//Output : d7 d6 d5 p4 d3 d2 d1
hamcode = {data_in[3:1] , p4 , data_in[0] , p2 , p1};
end
endmodule
Upvotes: 1
Reputation: 62037
It is unusual to use assign
within an always
block. You likely want to have the assign
outside the always
block to make your synthesis tool happy.
always @(*) begin
p1 = data_in[0] + data_in[1] + data_in[3];
p2 = data_in[0] + data_in[2] + data_in[3];
p4 = data_in[1] + data_in[2] + data_in[3];
// Input : d3 d2 d1 d0
//Output : d7 d6 d5 p4 d3 d2 d1
end
assign hamcode = {data_in[3:1] , p4 , data_in[0] , p2 , p1};
Upvotes: 2