CODEWITHSUNDEEP
armx86-64intelcpu-cacheamd-processor
Bogi
Bogi

Reputation: 2588

Prevent a CPU core from using the LL cache

I have a following problem: I have a low-latency application running on core 0, and a regular application running on core 1. I want to make sure that core 0 app gets as much cache as possible, therefore, I want to make core 1 bypass the L3 cache (not use it at all) and go directly in memory for data.

Are there any other ways I can achieve that core 0 app gets the priority in using the L3 cache?

Upvotes: 0

Views: 520

Answers (2)

northwindow
northwindow

Reputation: 343

On AMD Epyc: It would be good if you could move your low-latency application into an isolated core complex.

In Zen 2, 4 cores share a 16 MB slice of L3. In Zen 3, 8 cores share a 32 MB slice. Make sure your low-latency application is the only one that can touch the L3 slice of the core it's running on.

Upvotes: 1

Peter Cordes
Peter Cordes

Reputation: 363980

Some Intel CPUs support partitioning the L3 cache between different workloads or VMs, Cache Allocation Technology (CAT). It's been supported since Haswell Xeon (v3), and apparently 11th-gen desktop/laptop CPUs.

Presumably you need to let each workload have some L3, probably even on Skylake-Xeon and later where L3 is non-inclusive, but you might be able to give it a pretty small share and still achieve your goal.

More generally, https://github.com/intel/intel-cmt-cat has tools (for Linux and somewhat for FreeBSD) for managing that and other parts of what Intel's now calling "Resource Director Technology (RDT)" for monitoring, CAT, and Memory Bandwidth Allocation. It also has a table of features by CPU.

What you describe would be literally impossible on a desktop Intel CPU (or Xeon before Skylake), as they use inclusive L3 cache: a line can only be in L2/L1 if it's in L3 (at least tags, not the data if a core has it in Modified or Exclusive state). Skylake-X and later xeons have non-inclusive L3 so it would be possible in theory; IDK if CAT lets you give one set of cores zero L3.

I don't know if any AMD or ARM CPUs have something similar. I just happen to know of the existence of Intel's hardware support for this, not something I've ever gone looking for or used myself.

Upvotes: 3

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