CODEWITHSUNDEEP
system-veriloguvm
bu-ral
bu-ral

Reputation: 431

How to get the read signals in the sequence from driver in pipeline style UVM?

I'm trying to get read data (HRDATA) from a driver in the sequence or test. This is my driver:

////////// Pipelined UVM Driver //////////
class ahb_pipelined_driver extends uvm_driver #(ahb_seq_item);
  `uvm_component_utils(ahb_pipelined_driver)
  
  /// Virtual Interface
  virtual ahb_interface ahb_if;
  
  /// Constructor
  ....
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    ...
  endfunction

  
  forever begin
   
    ahb_if.HADDR <= req.HADDR;
    ahb_if.HWRITE <= req.HWRITE;
    ahb_if.HBURST <= req.HBURST;
  
  
  
  
    req.HRDATA = ahb_if.HRDATA;
    req.HRESP = ahb_if.HRESP;


    ahb_if.HWDATA <= req.HWDATA;
  end
  // Return the Request as Response
    seq_item_port.put(req);
    end_tr(req);
  end
  endtask: 
  
endclass:

I read the read data from req.HRDATA = ahb_if.HRDATA; in the driver, and I can check the value.

But, the problem is that I'd like to send read data to the sequence but this sequence immediately finished after I call seq_item_port.get() in the driver. So I can’t both wait for the read data to be available and have pipelined operation.

I want to send the read data to the sequence or test from the driver. How am I supposed to do that?

Upvotes: 1

Views: 829

Answers (1)

toolic
toolic

Reputation: 62073

You are not following the recommended UVM approach.

The driver should not sample the "read" data and check it. You should create a UVM agent with a driver and a monitor. The monitor should sample the read data and send it to a scoreboard for checking.

I recommend that you change your driver such that it no longer tries to sample the read data. Then create a UVM monitor which collects all AHB transactions (reads and writes) and sends them to a scoreboard.

See also:

Upvotes: 1

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