CODEWITHSUNDEEP
verilog
Tony
Tony

Reputation: 3

Why do I get red color for some signals in simulation?

I want to do manchester encoder's simulation in verilog. Design code and testbench codes are written. Although I don't get any error, in the simulation part "clk" and "data_out" are not working which is red color in simulation but reset and data_in are working in the simulation properly. How can I correct the issue?

module manchester_encoder(clk,reset,data_in,data_out);
input clk;
input reset;
input data_in;
output data_out;
integer prev_data;
  assign data_out = data_in ^ prev_data;
  always @(posedge clk) begin
    if (reset) begin
      prev_data <= 0;
    end else begin
      prev_data <= data_in;
    end
  end
  
endmodule

Its testbench

module testbench_manchester_encoder();
// Declare the signals
  reg clk;
  reg reset;
  reg data_in;
  wire data_out;
  
  // Instantiate the DUT
  manchester_encoder encoder(.clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out));
  
  // Generate the clock signal
  always #10 clk = ~clk;
  
  // Stimulus process
  initial begin
    reset = 1;
    data_in = 0;
    #20 reset = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 data_in = 1;
    #10 data_in = 0;
    #10 $finish;
  end
  
  // Monitor process
  always @(posedge clk) begin
    $display("Time=%t, data_out=%b", $time, data_out);
  end
endmodule

Upvotes: 0

Views: 346

Answers (1)

pschulz
pschulz

Reputation: 1535

You never initialize clk in your testbench, doing that fixes your problem:

module testbench_manchester_encoder();
// Declare the signals
  reg clk = 0; // <------- here
  reg reset;
  reg data_in;
  ...

Upvotes: 0

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