Reputation: 11
In my SystemVerilog test, I'm trying to make a task call name by using macros.
If AAA_BLK
is defined, I want the task call name replaced as test_aaa_proc();
, and the same way for BBB_BLK
and CCC_BLK
.
`ifdef AAA_BLK
`define BLK_NAME aaa
`elsif BBB_BLK
`define BLK_NAME bbb
`elsif CCC_BLK
`define BLK_NAME ccc
`endif
task test_aaa_proc();
...
endtask
task test_bbb_proc();
...
endtask
task test_ccc_proc();
...
endtask
virtual task body();
test_``BLK_NAME``_proc ();
endtask
But, it fails with below errors. Would you please advise?
test_``BLK_NAME``_proc ();
|
xmvlog: *E,EXPCPD
expecting a valid compiler directive [16(IEEE)].
test_``BLK_NAME``_proc ();
|
xmvlog: *E,MISEXX
expecting an '=' or '<=' sign in an assignment [9.2(IEEE)].
test_``BLK_NAME``_proc ();
|
xmvlog: *E,EXPCPD
expecting a valid compiler directive [16(IEEE)].
test_``BLK_NAME``_proc ();
|
xmvlog: *E,NOTDIR
`_proc: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
Upvotes: 1
Views: 182
Reputation: 62045
The ``
syntax can only be used in the macro definition, not in the macro call. Refer to IEEE Std 1800-2017, section 22.5.1 `define.
You can create a new macro which will resolve into the task name that you want to call. Then, you can call that new macro from the body
task. Here is a complete runnable example:
module tb;
`define AAA_BLK
`ifdef AAA_BLK
`define BLK_NAME aaa
`elsif BBB_BLK
`define BLK_NAME bbb
`elsif CCC_BLK
`define BLK_NAME ccc
`endif
`define TEST_TASK(block) test_``block``_proc
task test_aaa_proc();
$display("%m");
endtask
task test_bbb_proc();
$display("%m");
endtask
task test_ccc_proc();
$display("%m");
endtask
task body();
`TEST_TASK(`BLK_NAME);
endtask
initial body();
endmodule
This prints:
tb.test_aaa_proc
Upvotes: 0