CODEWITHSUNDEEP
cpu-architecturecpu-registersaccumulator
famesyasd
famesyasd

Reputation: 151

How does an accumulator register input work?

I'm reading through J Clark Skott's "But How Do It Know?" book that explains how cpu works using a very simple cpu example. All registers that are used in this book look like this: enter image description here

The question I have is about the ACC register shown on the picture below. enter image description here

Suppose the following: one of the following general purpose registers (e.g. R0) gets selected, we enable its output on the bus that goes into the "A" input of ALU and also select one type of one-operand operation 'op' that we want to do with it. The output of ALU flows into ACC register. However from this picture it seems that we can't choose to save it because the enabled output of R0 register also flows into ACC from the bus below it so if we choose to enable 's'ave bit I guess we will get two input bytes flowing into ACC register resulting in the unpredicted behaviour.

So my guess is that here it is meant that bus coming from the ACC register goes only one way - down to the general bus. Is my guess correct? If so, how do we implement it? This is a very minor question but it's been bugging me since it does not follow from his previous explanations in the book. From the first picture in my post all previous registers only had 2 bus-bytes coming for them - one for input and one for output and these two did not conflict because of 's', 'e' bits of registers. But here, this ACC register seems to have 3 bus-bytes: 2 inputs and 1 output that's why I'm a little confused here.

Upvotes: -1

Views: 413

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26656

Fundamentally, as the book explains in a chapter called "Doing Something Useful" on about page 80:

Let's say that we want to do something useful, like adding one number to another number. We have a number in R0, and there is another number in R1 that we want to add to the number in R0. The processor we have built so far has all of the connections to do this addition, but it will take more than one clock cycle to do it.

  • In the first clock cycle, we can enable R1 onto the bus, and set it into TMP.
  • In the second cycle we can enable R0 onto the bus, set the ALU to ADD, and set the answer into ACC.
  • In the third cycle, we can enable ACC onto the bus, and set it into Ro.

You are correct that should two registers be enabled at the same time (in your example, R0 and ACC), we would get either garbage on the bus — or a logical or'ing of the two bytes together.

The reason I suspect the logical or'ing if two registers were enabled, is that this is already what is happening when only one register is enabled to the bus.  The other registers are actually still connected to the bus, but they are each outputting a byte of 0's, so don't interfere with the register that is actually enabled.  Logical-or with zeroes is an identity function.

(I suppose it is remotely possible that the ACC may be capable of capturing output directly from I/O, but if that were possible you'd probably have to make sure that the ALU outputs zero to the ACC.)

Later in the book, it will explain how the stepper is used to accomplish those three cycles for some add instruction — several cycles are prepended to this sequence to fetch instructions (from RAM as programs are too large to fit in the CPU alone, they are stored in RAM and fetching the next instruction at proper time is an important feature of the processor; the processor will also need a program counter register (IAR) that refers to the next instruction in the stream, and, it will need to increment that program counter to get to the next instruction in the next set of cycles).

Though not this exact processor, Little Man Computer has a simulator where you can visualize the steps of a simple processor: https://www.peterhigginson.co.uk/LMC/

Upvotes: 2

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