What do I write in case statement choices if there is nothing to do?

Question

I'm doing this assignment:

Start out by implementing the simple version of code lock described in figure 4 using the interface described in figure 3. Use the three-process template to implement the state register, next state- and output process for the code lock. The "sync" is being supplied in a file and should be instantiated when implementing the VHDL ibd for the code_lock_simple. The purpose of the sync block is to provide a signal indicating either a rising- or a falling edge of the enter signal. The signal will be synchronized to the clk signal. b) Create a functional simulation of your design, just as you did with the Mee-Moo state machine. Does the state change happen as expected? Add simulation waveform to your journal. c) Create a tester and test your design on the DE2-board, with an interface as in figure 5

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;

entity code_lock_simple is
    port(
            clk : in std_logic;
            reset : in std_logic;
            code : in std_logic_vector(3 downto 0);
            enter : in std_logic;
            -- Lock output
            lock : out std_logic
            );
            
end code_lock_simple;

architecture Behavioral of code_lock_simple is

        type state_type is (Unlocked, Idle, Ev_code1, Get_code2, Ev_code2, Wrong_code, Perm_locked); 
        
        signal present_state, next_state : state_type; 
        
    begin
    state_reg : process (clk, reset)
    begin
        if rising_edge(clk) then
            if reset = '0' then 
                present_state <= Idle;
            else
                present_state <= next_state; 
            end if;
        end if;
    end process; 
    
    outputs : process (present_state, enter, code)
        constant code1 : std_logic_vector(3 downto 0) := "1111";
        constant code2 : std_logic_vector(3 downto 0) := "0000";
        
begin
case present_state is 

     when Idle =>
         if enter = '1' then 
        lock <= '1'; 
      end if; 
    
    when ev_code1 =>
        if enter = '1' and code = code1 then
            lock <= '1';
        elsif enter = '1' and code /= code1 then 
            lock <= '1';
        end if; 
        
    when get_code2 => 
        if enter ='1' then 
            lock <= '1'; 
        end if; 
    
    when ev_code2 => 
        if enter = '1' and code /= code2 then
            lock <= '1';
        elsif enter = '1' and code = code2 then
            lock <= '1'; 
        end if; 
    
    when unlocked => lock <= '0'; 
        if enter = '1' then
            lock <= '1';
        end if;
    end case; 
end process; 

  

                 
        
            
-- NEXT STATE PROCESS
    

------ Hardwirede koder til kodelåsen
 nxt_state : process (present_state, code, enter) 

    constant code1 : std_logic_vector := "1100"; 
    constant code2 : std_logic_vector := "1110";
    
     begin
    
        next_state <= present_state; 
        
        
        case present_state is 
            
            when Idle =>
                if enter = '1' then 
                    next_state <= ev_code1;
                end if; 
            
            when ev_code1 =>
                    if enter = '1' and code = code1 then
                    next_state <= ev_code2;
                    elsif enter = '1' and code /= code1 then 
                        next_state <= Idle; 
                    end if;
            
            when get_code2 =>
                if enter = '1' then 
                    next_state <= ev_code2; 
                end if;
                
            when ev_code2 => 
                if enter = '1' and code /= code2 then 
                    next_state <= Idle; 
                    
                elsif enter = '1' and code = code2 then 
                    next_state <= unlocked; 
                end if; 
            
            when unlocked => lock <= '0'; 
                if enter = '1' then 
                    next_state <= Idle; 
                end if;     
            
            when others =>
                next_state <= Idle; 
        end case;
    end process; 
end; 

I get this error:

Error (10313): VHDL Case Statement error at code_lock_simple.vhd(41): Case Statement choices must cover all possible values of expression

How should I write this and what should the code look like?

when Unlocked =>
  -- do something here
when Get_code1 =>
  -- do something here
when Wrong_code =>
  -- do something here
when Perm_locked =>
  -- do something here

Answer 1

The case statement in the outputs process does not cover all possble values for present_state. This is especially nasty in a combinatorial process like outputs, because it will infer latches.
One way to solve this is to add a others => case, similar to how it is done in the nxt_state process.

To explicitly do nothing the null statement can be used. However if this is the correct behavior is up to you to decide (depending on how the circuit is supposed to behave).

Either

outputs : process (present_state, enter, code)
...
begin
case present_state is 
...
when others => null;
end case;
...

Or alternatively all missing choices can be listed explicitly

outputs : process (present_state, enter, code)
...
begin
case present_state is 
...
when Unlocked | Get_code1 | Wrong_code | Perm_locked => null;
end case;
...

Answer 2

My VHDL is a tad rusty, but this error is pointing to your case statement not covering every state you defined for a signal of 'state_type' in this line:

type state_type is (Unlocked, Idle, Ev_code1, Get_code2, Ev_code2, Wrong_code, Perm_locked);

To resolve the issue, you'll need to add cases for Unlocked, Get_code1, Wrong_Code, and Perm_locked.

You'll want to cover this in both instances of your case statement.