CODEWITHSUNDEEP
scalachiselscala-2.12
KFaidon K.
KFaidon K.

Reputation: 67

How to bulk connect IO bundles in chisel? How does BiConnect work?

I struggle to understand the documentation around the <> operator in chisel but I have managed to something like this successfully, so I thought I had some understanding of it:

      fetchStage.io.f2d <> decodeStage.io.f2d

where

    class DecodeStage extends Module {
      val io = IO(new Bundle {
        val f2d = new Bundle {
          val pc = Input(UInt(16.W))
          val instruction = Input(UInt(16.W))
        }
      })
    ...
    
    class FetchStage extends Module {
      val io = IO(new Bundle {
        val branch = new Bundle {
          val enable = Input(Bool())
          val pc = Input(UInt(16.W))
        }
        val f2d = new Bundle {
          val pc = Output(UInt(16.W))
          val instruction = Output(UInt(16.W))
        }
      })
    ...

However when I do this:

     fetchStage.io.branch <> executeStage.io.branch

where

    class ExecuteStage extends Module {
      val io = IO(new Bundle {
        val branch = new Bundle {
          val enable = Output(Bool())
          val pc = Output(UInt(16.W))
        }
      })

I get the following error:

    [error] chisel3.internal.ChiselException: Connection between left (FetchStage.io.branch: IO[AnonymousBundle]) and source (FetchStage_1.io.branch: IO[AnonymousBundle]) failed @.pc: Neither Left nor Right is a driver
    [error]         at ... ()
    [error]         at Elidon.<init>(Main.scala:27)
    [error]         at Main$.$anonfun$new$8(Main.scala:42)
    [error]         at ... ()
    [error]         at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace)
    [error] stack trace is suppressed; run last Compile / run for the full output
    [error] (Compile / run) chisel3.internal.ChiselException: Connection between left (FetchStage.io.branch: IO[AnonymousBundle]) and source (FetchStage_1.io.branch: IO[AnonymousBundle]) failed @.pc: Neither Left nor Right is a driver

Could you help me understand what is going on please? Is there another way to achieve the desired behaviour without connecting all fields one by one?

Upvotes: 2

Views: 128

Answers (1)

KFaidon K.
KFaidon K.

Reputation: 67

This is not a solution or explanation, just a workaround that I figured out. Since FetchStage only has inputs and ExecuteStage only has outputs, I could just as easily do:

fetchStage.io.branch := executeStage.io.branch

Which works...

Upvotes: 0

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