CODEWITHSUNDEEP
verilogsystem-verilogsystem-verilog-assertions
sreekesh padmanabhan
sreekesh padmanabhan

Reputation: 45

Parameter within module name

I'm writing a module assertion bind:

module top_assertion #(parameter WIDTH=8) (input rtl_signal);

axi_``WIDTH``_bus axi_bus;

assert property (@(posedge Clock) !$isunknown(axi_bus.valid);

endmodule

bind rtl_module top_assertion#(8) assertion(.*);

Idea being using different axi_buses (Ex: axi_8_bus, axi_32_bus, axi_64_bus interfaces) depending on what WIDTH parameter is passed. I could write with axi_8_bus, axi_32_bus, axi_64_bus instances explicitly hardcoded but I want it to be dynamic instead.

It seems axi_``WIDTH``_bus isn't valid though.

Could anyone help please?

Upvotes: 1

Views: 113

Answers (1)

toolic
toolic

Reputation: 62236

The `` syntax is used with define compiler macros, not parameters.

You could use a generate construct with a case statement to conditionally declare the interface you need based on the parameter value:

module top_assertion #(parameter WIDTH=8) ();

case (WIDTH)
    8 : axi_8_bus  axi_bus ();
    32: axi_32_bus axi_bus ();
    64: axi_64_bus axi_bus ();
endcase

//..(assertion checks on axi_bus)..

endmodule

Refer to IEEE Std 1800-2017, section 27.5 Conditional generate constructs. The generate keyword is optional.

Upvotes: 1

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