CODEWITHSUNDEEP
embeddedriscvtoolchaingnu-toolchainriscv32
K.Mulier
K.Mulier

Reputation: 9620

Where is the source code from the WCH RISC-V toolchain?

WCH, the company behind the famous 10-cent RISC-V microcontroller, has based its RISC-V toolchain on the xPack builds from Liviu Ionescu: https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/tag/v8.2.0-3.1/

Both output the same version string:

riscv-none-embed-gcc.exe (xPack GNU RISC-V Embedded GCC, 32-bit) 8.2.0
Copyright (C) 2018 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

However, there are some minor differences between the RISC-V toolchain from WCH and the one from xPack. The WCH toolchain supports a few more RISC-V instruction sets, like:

 
Question 1:
The 'w' and 'x' letters are non-standard RISC-V extensions. What do they stand for?

 
I also notice that the WCH toolchain has the following libraries that don't appear anywhere in the native xPack toolchain:

 
Question 2:
What are these non-standard libraries for? I was able to build a sample project with both the WCH toolchain and the native xPack toolchain. In both cases, the printf() function worked just fine, sending characters over the TX line. So I wonder what the libprintf.a library is used for, if the setup works without that library?

 
Question 3:
Where can I find the source code of the WCH toolchain, and the build instructions?

Thank you very much.

Upvotes: 4

Views: 652

Answers (1)

Charlie
Charlie

Reputation: 271

A1:

From page 2, Chapter 1.1 of the QingKeV2 Processor Manual (note that "V2A" is the WCH designation for their RTL realization of the RISC-V ISA used in the CH32V003)

  • XW: 16-bit compression instruction for self-extending byte and half-word operations Note: To further improve code density, extend the XW subset by adding the following compression directives c.lbu/c.lhu/c.sb/c.sh/c.lbusp/ c.lhusp/c.sbsp/c.shsp, use based on the MRS compiler or the toolchain it provides.

Note: Something not mentioned in your question, that is modified behavior from the link, is the fact that the CH32V family (being microcontrolers) have optimized interrupt hardware that has integrated CPU/compiler support. Particularly, they have a fast call scheme that shadows critical registers when a call is invoked. This reduces latency because it does not have to push return addresses to the stack. Useful for real time applications.

A2:

The first library is an RV optimized math library. It is essentially a float-fixed implementation that provides some interchange between the two. It is "inspired by" Texas Instruments® C28x IQmath Library.

Near as I can tell, the other two of those libraries separate out integer and floating point from the original routine. This makes printf() lighter for most tasks... unless you need to use the %f feature. (You should note that, although it compiles and works mostly as expected, specifically %f does not actually work.)

A3:

This is the real issue. Indeed, the source project that WCH used is covered under the GPL. Indeed, WCH/MRS took that source, modified it, and released the product binary. Under the GPL, they should be compelled to provide the source upon request under the protections of the license.

I am not an authority on the PRC, so I can't say with certainty what the GPL license means to them. However, a quick search on the web suggests "not much."

Upvotes: 1

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