CODEWITHSUNDEEP
fpgaquartus
james
james

Reputation: 21

FPGA Max 10 DE10 Lite Board Error (169026) on Quartus 22.1 VHDL

I am trying to implement the project https://www.youtube.com/watch?v=50EC76bpkQI

When I try to compile the Quartus II, it gives me the following errors:

Error (169026): Pin myLEDR[1] with I/O standard assignment 3.3-V LVTTL is incompatible with I/O bank 7. I/O standard 3.3-V LVTTL, has a VCCIO requirement of 3.3V, which incompatible with the I/O bank's VCCIO setting or with other output or bidirectional pins in the I/O bank using a VCCIO requirement of 2.5V. Assign output and bidirectional pins with different VCCIO requirements to different I/O banks, or change the I/O standard assignment for the specified pin to a compatible I/O standard. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
    Info (169073): Pin myLEDR[0] in I/O bank 7 uses VCCIO 2.5V
Warning (169177): 10 pins must meet Intel FPGA requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing MAX 10 Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.
    Info (169178): Pin mySW[0] uses I/O standard 3.3-V LVTTL at C10
    Info (169178): Pin mySW[1] uses I/O standard 3.3-V LVTTL at C11
    Info (169178): Pin mySW[2] uses I/O standard 3.3-V LVTTL at D12
    Info (169178): Pin mySW[3] uses I/O standard 3.3-V LVTTL at C12
    Info (169178): Pin mySW[4] uses I/O standard 3.3-V LVTTL at A12
    Info (169178): Pin mySW[5] uses I/O standard 3.3-V LVTTL at B12
    Info (169178): Pin mySW[6] uses I/O standard 3.3-V LVTTL at A13
    Info (169178): Pin mySW[7] uses I/O standard 3.3-V LVTTL at A14
    Info (169178): Pin mySW[8] uses I/O standard 3.3-V LVTTL at B14
    Info (169178): Pin mySW[9] uses I/O standard 3.3-V LVTTL at F15
Error: Quartus Prime Fitter was unsuccessful. 10 errors, 5 warnings
    Error: Peak virtual memory: 4977 megabytes
    Error: Processing ended: Sat Jun 10 17:34:53 2023
    Error: Elapsed time: 00:00:02
    Error: Total CPU time (on all processors): 00:00:02
Error (293001): Quartus Prime Full Compilation was unsuccessful. 12 errors, 6 warnings

I am listing only one error. There are 9 similar errors.

Is there a problem with the voltage levels set? I have tried changing them to 2.5-V and 3.0-V but this results in more errors.

Thanks in advance.

James

Upvotes: 0

Views: 339

Answers (1)

james
james

Reputation: 21

I had made a small mistake in my assignment. myLED[0] was mispelled as my_myLED[0] and this made the whole compilation crush.

Now its sorted and working as it should be.

//James

Upvotes: 0

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