scala process never finishes in IDEA

Question

When I running a SpinalHDL simulation program, the process is done but never exit. That is, "Process finished with exit code 0" never showed up. I have to shutdown the IDEA to end the process. How is it?

import spinal.core._
import spinal.sim._
import spinal.core.sim._

import scala.util.Random


//MyTopLevel's testbench
object MyTopLevelSim {
  def main(args: Array[String]) {
    SimConfig.withWave.doSim(new MyTopLevel){dut =>
      //Fork a process to generate the reset and the clock on the dut
      dut.clockDomain.forkStimulus(period = 10)

      var modelState = 0
      for(idx <- 0 to 99){
        //Drive the dut inputs with random values
        dut.io.cond0 #= Random.nextBoolean()
        dut.io.cond1 #= Random.nextBoolean()

        //Wait a rising edge on the clock
        dut.clockDomain.waitRisingEdge()

        //Check that the dut values match with the reference model ones
        val modelFlag = modelState == 0 || dut.io.cond1.toBoolean
        assert(dut.io.state.toInt == modelState)
        assert(dut.io.flag.toBoolean == modelFlag)

        //Update the reference model value
        if(dut.io.cond0.toBoolean) {
          modelState = (modelState + 1) & 0xFF
        }
      }
    }
  }
}

Belows are the infomation in Console. The process is never ending...

Connected to the target VM, address: '127.0.0.1:57888', transport: 'socket'
[Runtime] SpinalHDL v1.6.0    git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
[Runtime] JVM max memory : 4070.0MiB
[Runtime] Current date : 2023.06.21 15:11:03
[Progress] at 0.000 : Elaborate components
[Progress] at 0.611 : Checks and transforms
[Progress] at 0.685 : Generate Verilog
[Done] at 0.755
[Progress] Simulation workspace in C:\Users\xxx\spinalhdl_home\test_new\.\simWorkspace\MyTopLevel
[Progress] Verilator compilation started
[Progress] Verilator compilation done in 4973.795 ms
[Progress] Start MyTopLevel test simulation with seed 835369353
done1
[Done] Simulation done in 20.747 ms

Find the problem in SpinalHDL simulation with verilator in my own PC, while in others' PCs it is done well. How to end the process as a general program process?