how to config I2S master clock in STM32F730?

Question

I want to change MCLK f_s rates for 44100 sample rate audio on STM32F703.

Right now my clock in STM32 is 207.36MHz

I2S PLL values: N=147, R=2, Q=2 and PLLI2SDivQ=10

I2S clock is supplied with PLLI2SR which clock is 112.896.

I have changed PLLI2SDivQ values but it doesn't affect the I2S MCLK clock I have observed it on Oscilloscope and its 112.896MHz even when PLLI2SDivQ is 10 or 5

Answer 1

The I2S clock determines the bit rate, not the sample_rate for for 44.1ksps 16 bit stereo, you would need a bit rate of 1.4112x10⁶bps

The clock rate generator is as follows:

^{Ref: STM32F72xx/3xx RM0431}

With your stated configuration I²SxCLK is 11.2896MHz

And the sample rate is calculated per:

^{Ref: STM32F72xx/3xx RM0431}

So for 44.1ksps you need the denominator in the appropriate formula above to be 11.2896MHz / 44.1ksps = 256

So for I2S mode 16-bit x 2, MCKOE=0:

32 x ((2 × I2SDIV) + ODD) = 256 is achieved when I2SDIV = 4 and ODD=0.