CODEWITHSUNDEEP
bit-manipulationverilogbitwise-operatorsbitwise-andbitwise-or
superb ranjeet
superb ranjeet

Reputation: 33

how to perform bit wise "or" operation with same value/ variable?

I am trying to understand bitwise operation that took place in same variable within itself. let's say i have 2 variable x which is 4-bit reg type, if i write

w_out<=(|x); you can take value of x as 15

what will be the value of w_out ?.

my next doubt is related to extension of my first question: -

I have given some project code to understand and when I analyse the verilog code I got stuck at one point. I am giving you a code snippet which you can look in better way.

if(crc_flag)
            begin
                modem_fifo_in_data <= {crc_calc,16'd0}.
                modem_wren <= 1;
            end
        else
            begin
                modem_fifo_in_data <= dout_120M_r02;

                **modem_wren <= (|dout_valid_120M_r02) && rden_120M_r04**;

            end

i have a problem to understand the bold parts of code: -

modem_wren <= (|dout_valid_120M_r02) && rden_120M_r04

Here, dout_valid_120M_r02 is 4-bit reg type data, rden_120M_r04 is 1-bit reg type data.

Now how exactly the operation (|dout_valid_120M_r02) took place and then logical AND operation will take place?

this is related to given code snippets

I just want to know how within same variable bitwise operation take place.

specially this - modem_wren <= (|dout_valid_120M_r02) && rden_120M_r04

how we can perform bitwise operation modem_wren_new <= (|dout_valid_120M_r02) you can take any 4-bit value like 15, its upto you.

Upvotes: -2

Views: 442

Answers (2)

Tushar
Tushar

Reputation: 499

w_out<=(|x); This means w_out will be 1 if any of the bit(s) of signal x is 1. bitwise OR as the name suggests perform the logical OR operation on all the bits of the signal on the right hand side. For example, if:

reg [3:0] x; //x is a 4-bit signal
assign w_out = |x; // equivalent of w_out = x[3] || x[2] || x[1] x[0];

For the second part: modem_wren <= (|dout_valid_120M_r02) && rden_120M_r04,
modem_wren will be 1 when rden_120M_r04 = 1'b1 AND any bit of dout_valid_120M_r02 is 1.

Upvotes: -1

EEliaz
EEliaz

Reputation: 359

The answer to your first question is that the value of w_out will be 1'b1.

The operation (|something) is equivalent to OR all the bits of "something" together:

(|something) <==> something[0] | something[1] | something [2] | ...

So basically the operation in your example is checking if any bit of "x" is set to 1'b1.

BTW, this can be performed also with other operators, such as XOR and AND:

(^something) <==> something[0] ^ something[1] ^ something [2] ^ ...
(&something) <==> something[0] & something[1] & something [2] & ...

Now, I believe this answers also your second question. The next line:

modem_wren <= (|dout_valid_120M_r02) && rden_120M_r04

Indicates the next logic:

"is there any bit set to 1'b1 in dout_valid_120M_r02, and rden_120M_r04==1'b1? If so, set modem_wren to 1'b1. Otherwise, set it to 1'b0".

Notice that the answer to "is there any bit set to 1'b1 in dout_valid_120M_r02" is a 1 bit (boolean) answer. Either there is a bit set to 1'b1, or not.

Therefore, what happens in this equation, is that you OR all the bits of dout_valid_120M_r02, which results in a single bit, which you then AND with rden_120M_r04.

Let's do an actual example to emphasize the behavior. Assume:

dout_valid_120M_r02==4'b0100;
rden_120M_r04==1'b0;

Then:

(|dout_valid_120M_r02) == (|4'b0100) == 1'b0 | 1'b1 | 1'b0 | 1'b0 == 1'b1

And finally:

(|dout_valid_120M_r02) && rden_120M_r04 == 1'b1 && 1'b0 == 1'b0

Upvotes: -1

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