CODEWITHSUNDEEP
verilogsystem-verilogassertionformal-verificationsystem-verilog-assertions
Amala Joseph
Amala Joseph

Reputation: 21

SVA assertion compile syntax errors

assert property @(posedge(clk)) !rstN |-> n==0 && full==0 && empty==1;
assert property @(posedge clk) disable iff(!rstN) ( full |=>(wr_en  && $stable (n) ) );
assert property @(posedge clk) disable iff(!rstN) (empty |=>(rd_en && $stable (n)) );

The errors shows near @ and full, empty.

Shows syntax error near "(" which is near to full and empty, syntax error near all @.

Where am I going wrong?

Upvotes: 2

Views: 191

Answers (1)

toolic
toolic

Reputation: 62236

You need to add parentheses for the property code. Refer to IEEE Std 1800-2017, section 16.12 Declaring properties for code examples.

This is a complete code example that compiles without syntax errors:

module tb;
   bit clk, rstN, n, full, empty;
   assert property (@(posedge(clk)) !rstN |-> n==0 && full==0 && empty==1);
endmodule

Upvotes: 1

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