Verilog BRAM sorting

Question

I want to infer 8x4 Single port BRAM in Verilog, and I have to read the values of the RAM and sort them. In the sorting process, I need to sort the RAM data from smallest to largest by writing to the lowest memory addresses. However, I got some errors in Verilog, and I could not understand them. Here is my Verilog BRAM code.

`timescale 1ns / 1ps

module DS(
 input clk, // clock signal
 input [2:0] ram_addr, // RAM address input
 input [3:0] ram_data_in, // RAM data input
 output reg [3:0] ram_data_out, // RAM data output
 input ram_we // RAM write enable
    );

// Declare RAM array
reg [3:0] ram [0:7];

// Define RAM behavior
always @(posedge clk) begin
    if (ram_we) begin
        ram[ram_addr] <= ram_data_in; // write to RAM
    end
    ram_data_out <= ram[ram_addr]; // read from RAM
end   
    
endmodule

Here is my Sort_mem (sorting process) module:

`timescale 1ns / 1ps

module Sort_mem(
 input clk, // clock signal
 output reg [3:0] min, // minimum value
 output reg [2:0] min_addr, // minimum value address
 output [3:0] ram_out, // RAM output
 input [3:0] ram_in, // RAM output
 input [2:0] ram_addr,
 input ram_we 
    );
// Declare RAM signals

reg [3:0] ram_data_in; // RAM data input
reg [3:0] out; // RAM data output
reg write; // RAM write enable
reg [2:0] ADRES;
// Instantiate RAM module
DS ds_inst(
    .clk(clk),
    .ram_addr(ADRES),
    .ram_data_in(ram_data_in),
    .ram_data_out(out),
    .ram_we(write)
);

// Define sort logic
reg [3:0] counter; // loop counter
always @(posedge clk) begin
    // Initialize min, min_addr and counter
    min <= ram_data_out;
    min_addr <= 0;
    counter <= 0;
    // Use case statement to loop through RAM elements
    case (counter)
        0: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 0;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        1: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 1;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        2: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 2;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        3: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 3;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        4: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 4;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        5: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 5;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        6: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 6;
            end
            // Increment counter and address
            counter <= counter + 1;
            ADRES <= counter;
        end
        7: begin
            // Update min and min_addr if needed
            if (ram_data_out < min) begin
                min <= ram_data_out;
                min_addr <= 7;
            end
            // Write min to lowest RAM address
            write <= 1;
            ram_data_in <= min;
            ADRES <= 0;
            // Reset counter and write enable
            counter <= 0;
            write <= 0;
        end
    endcase
end
assign ram_in = ram_data_in;
assign ram_out = ram_data_out;

endmodule

and here is the testbench

`timescale 1ns / 1ps

module test();
reg clk;
reg yaz;
reg adres;
reg data;
reg out;

Sort_mem uut(.clk(clk),.ram_we(yaz),.ram_addr(adres), .ram_in(data), .ram_out(OUT));
always
begin
    #5
    clk <= ~clk;
end
initial
begin
    clk <= 0;   
    yaz <= 0;
    adres <= 0;
    data <= 0;

    #10

    yaz <= 1;
    adres <= 7;
    data <= 7;
   
    #10
    adres <= 6;
    data <= 4;
   
    #10
    adres <= 5;
    data <= 9;

    #10
    adres <= 4;
    data <= 3;
    #10
    adres <= 3;
    data <= 3;
     #10
    adres <= 2;
    data <= 3;
    
     #10
    adres <= 1;
    data <= 3;
     #10
    adres <= 0;
    data <= 3;
    #10
    yaz <= 0;
    #40
    $finish;
end
endmodule

Here is the errors

[USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Vivado Project/BRAM_DENEME/BRAM_DENEME.sim/sim_1/behav/xsim/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

The visible errors in my code just on this "`timescale 1ns / 1ps" and it is "Error: Parsing info not available during refresh".

I have to perform the sorting process without using a for loop.

I tried converting ram_out reg to wire. I expected to see the simulation screen and the sorted values, but I could not.

Verilog BRAM sorting

Answers (1)

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