CODEWITHSUNDEEP
cpu-architectureprivilegesriscv
Ömer GÜZEL
Ömer GÜZEL

Reputation: 163

How exception occurred in debug mode do end execution of program buffer in RISCV architecture?

The below quotation is taken from riscv-debug-spec version 0.132.

  1. Exceptions don’t update any registers. That includes cause, epc, tval, dpc, and mstatus. They do end execution of the Program Buffer.

I understand the exceptions do not update the mentioned CSRs. However, I couldn't understand how it does end the program buffer. It is not clearly defined. Should I count the exception as dret instruction in debug mode? or should I send the exception information to the Debug Module that will take care of ending the execution buffer?

Upvotes: 0

Views: 155

Answers (1)

Yang Ding
Yang Ding

Reputation: 1

If I understand you correctly, you want to use progbuf to access memory or register.After you execute the instructions stored in progbuf, you need to end the progbuf run.With progbuf operations, programs must end with the instruction ebreak, which terminates the execution of the program buffer. Ebreak is an instruction, encoded 0x100073, that interrupts the operation of a program so that the system can hand over the use to the Debugger. By the way, executing the dret instruction in the program buffer results in undefined behavior.

Upvotes: 0

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