How do I modify this .hdl chip to fulfill the question's requirements? (boolean logic / nand2tetris)

Question

CHIP FALL {
    IN A, B, C, D, f0, f1;
    OUT E, F, G;

    PARTS:
    // Implement FZero
    FZero(A=A, B=B, C=C, D=D, F=zF, G=zG);

    // Implement FOne
    FOne(A=A, B=B, C=C, D=D, F=oF, G=oG);

    // Implement FTwo
    FTwo(A=A, B=B, C=C, D=D, F=tF, G=tG);

    // Implement FThree
    FThree(A=A, B=B, C=C, D=D, E=thE, F=thF, G=thG);

    Mux(a=thF, b=tF, sel=f0, out=iF1);
    Mux(a=oF, b=zF, sel=f0, out=iF2);
    Mux(a=iF1, b=iF2, sel=f1, out=F);

    Mux(a=thG, b=tG, sel=f0, out=iG1);
    Mux(a=oG, b=zG, sel=f0, out=iG2);
    Mux(a=iG1, b=iG2, sel=f1, out=G);

    Mux(a=thE, b=false, sel=f0, out=iE1);
    Mux(a=iE1, b=false, sel=f1, out=E);

}

Question:

Adapt the circuit FALL so that it can combine a sequence of operations defined by different values for f1 and f0 at each step, by enabling the outputs Ft and Gt of step t to be used (feedback) as the inputs for the next operation Ct+1 and Dt+1 for step t + 1. You should also add a further input (Load) to the chip which when Load = 1 will enable you to load new inputs to Ct and Dt and when set to 0 sets Ct+1 = Ft and Dt+1 = Gt. The Load input will allow you to manually set the values of C and D at the start and during the sequence if required. Call this chip FSEQ.

You must only use the built-in AND, NAND, OR, NOR, NOT, Mux, DMux,XOR or DFF chips.

I'm a 1st year comp sci student and I'm not sure how to progress with this question. I've tried building it myself to no avail