VHDL-clock simulation, 80 ps delay

Question

I am new to VHDL and I created a 25% duty cycle 10 kHz clock from a 100 MHz 50% duty cycle clock, but when I simulate it, there is a 80 ps delay between every rising edge of the clocks. What causes this and how can I fix it?

I created a 10 MHz clock using clocking wizard and added it to my topmodule.

Simulation:

Simulation zoomed out:

topmodule:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity waveform is
Port (clk_in: in std_logic;
     clk_out: out std_logic );
end waveform;

architecture Behavioral of waveform is
    signal clk_out1 : std_logic;
    signal reset : std_logic;
    signal locked : std_logic;
    signal clk : std_logic:='1';
    signal ctr: integer range 0 to 999:=0;
    
    
    component clk_wiz_0
    port (
        -- Clock in ports
        -- Clock out ports
        clk_out1          : out    std_logic;
        -- Status and control signals
        reset             : in     std_logic;
        locked            : out    std_logic;
        clk_in            : in     std_logic
    );
    end component;

begin
    clk_wiz: clk_wiz_0
    port map ( 
        -- Clock out ports  
        clk_out1 => clk_out1,
        -- Status and control signals                
        reset => reset,
        locked => locked,
        -- Clock in ports
        clk_in => clk_in
    );

    process(clk_out1)
    begin
        if rising_edge(clk_out1) then
            ctr <= ctr + 1;
            if ctr = 249 then 
                clk <= not clk;
            elsif ctr = 999 then
                clk <= not clk;
                ctr <= 0;
            end if;
        end if;
  
        clk_out<=clk;
    end process;

end Behavioral;

simulation:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testbench_waveform is
end testbench_waveform;

architecture Behavioral of testbench_waveform is
    -- Constants
    constant CLK_PERIOD : time := 10 ns;  

    -- Signals
    signal clk_in : std_logic := '0';  -- Input clock signal
    signal clk_out : std_logic;        -- Output clock signal from the waveform module

    -- Component declaration
    component waveform
        port (
            clk_in : in std_logic;
            clk_out : out std_logic
        );
    end component;

begin
    -- Instantiate the waveform module
    UUT: waveform
    port map (
        clk_in => clk_in,
        clk_out => clk_out
    );

    -- Clock process for generating clk_in
    clk_process: process
    begin
        while now < 100000000 ns loop  -- Simulate for 1000 ns
            clk_in <= not clk_in;  -- Toggle the clock signal
            wait for CLK_PERIOD / 2;  -- Wait for half the clock period
        end loop;
        wait;  -- Wait indefinitely after simulation completes
    end process;

end Behavioral;