CODEWITHSUNDEEP
verilog
kavita
kavita

Reputation: 19

Verilog code output is always zzz using carry lookahead adder

I am trying to make a multiplier using carry lookahead adder, but the half of my output is zzzz. Here is a part of my code. The cla16 is a 16-bit carry lookahead adder. It is producing zz at output in v16bit module.

module v16bit(a,b,p);
  input [15:0] a,b;
  output [31:0] p;
  wire [15:0] p1,p2,p3,p4;
  wire [17:0] s1,s2;
  v8bit adabudi(a[7:0],b[7:0],p1);
  v8bit sjubh(a[15:8],b[7:0],p2);
  v8bit csfc(a[7:0],b[15:8],p3);
  v8bit cucbu(a[15:8],b[15:8],p4);
  
  assign p[7:0]= p1[7:0];
  csa16bit bubsuf(p2,p3,{8'b0,p1[15:8]},s1);
  assign p[15:8]=s1[7:0];
 // cla16 consn(p4, s1[17:8],s2);
  cla16 consn(p4, {6'b0,s1[17:8]},s2); //////{THIS PART IS PRODUCING ZZZ AT OUTPUT}

  assign p[31:16]=s2[15:0];
endmodule

module cla16(a,b, cin, sum);
input [15:0] a,b;
input cin;
output [15:0] sum;
//output cout;
wire c1,c2,c3,c4;

cla4 cla1 ( a[3:0] , b[3:0], 1'b0,  sum[3:0] ,  c1)  ;
cla4 cla2 ( a[7:4] , b[7:4], c1,  sum[7:4] ,  c2)  ;
cla4 cla3( a[11:8] , b[11:8], c2,  sum[11:8] ,  c3)  ;
cla4 cla6( a[15:12] , b[15:12], c3,  sum[15:12] ,  c4)  ;
endmodule

module cla4(a,b, cin, sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;

wire [3:0] p,g,c;

assign p=a^b;//propagate
assign g=a&b; //generate

//carry=gi + Pi.ci

assign c[0]=cin;
assign c[1]= g[0]|(p[0]&c[0]);
assign c[2]= g[1] | (p[1]&g[0]) | p[1]&p[0]&c[0];
assign c[3]= g[2] | (p[2]&g[1]) | p[2]&p[1]&g[0] | p[2]&p[1]&p[0]&c[0];
assign cout= g[3] | (p[3]&g[2]) | p[3]&p[2]&g[1] | p[3]&p[2]&p[1]&g[0] | p[3]&p[2]&p[1]&p[0]&c[0];
assign sum=p^c;
endmodule

This is the output

I don't understand why high impedance is showing at the output. Please help me if you can locate any error.

Upvotes: 1

Views: 63

Answers (1)

toolic
toolic

Reputation: 62236

Your code has a port connection error on that line. Your simulator should have reported this as a compile warning; check your log files. If it did not, consider using a different simulator, like the ones on edaplayground.

The cla16 module has 4 ports, but you only made connections to 3 of them in the consn instance.

You used connection-by-order. This means that s2 is connected to the cin input port of cla16. You declared s2 as a wire, which means its default value is z. Since you connected it to an input port, it is not driven, which means it remains at z for the entire simulation. Since the 16 MSBs of p are driven by s2, they are also z.

You should use connection-by-name to avoid this common Verilog error:

cla16 consn (
    .sum (s2), // assuming you want s2 to be connected to sum
    .a   (p4),
    .b   (), // make connection here
    .cin ()  // make connection here
);

Upvotes: 2

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