error message chisel when call a module in another module

Question

I have defined the class fu_data_t and cap_result_t in a scala file, which is used in the class crevokeModule in another scala file. Then, crevokeModule is used in the class AluDataModule. Finally, AluDataModule is used in another class. All in same scala file. is it necessary to add any header to second scala file? I received below error...

Here is the relevant code:

class  cap_result_t extends Bundle{
    val cap  = clen_t
    val tag   = UInt (1.W)
    val valid   = UInt (1.W)
   }
class  fu_data_t extends Bundle{
    val operand_a = UInt (XLEN.W)
    val operand_b = UInt (XLEN.W)
    val imm       = UInt (XLEN.W)
    val cap_a     = clen_t
    val cap_b     = clen_t
    val cap_c     = clen_t
    val tag_a     = UInt (1.W)
    val tag_b     = UInt (1.W)
    val tag_c     = UInt (1.W)
    val valid     = UInt (1.W) 
    val rd        = UInt (5.W)
    val rs1       = UInt (5.W)
    val rs2       = UInt (5.W)

   }



class AluDataModule(implicit p: Parameters) extends XSModule {
  val io = IO(new Bundle() {
    val src = Vec(2, Input(UInt(XLEN.W)))
    val func = Input(FuOpType())
    val pred_taken, isBranch = Input(Bool())
    val result = Output(UInt(XLEN.W))
    val taken, mispredict = Output(Bool())
 
    val fu_data_curt  = Input(new fu_data_t)
    val rd_result_ot  = Output(new cap_result_t )
  })
  val (src1, src2, func) = (io.src(0), io.src(1), io.func)
  // val fu_data_curtt = fu_data_curt
  val fu_data_curtt = io.fu_data_curt

With this structure I get the error below. Can someone help me fix this error?

class crevokeModule extends Module {
   val io = IO(new Bundle() {
   val src = Input(UInt(XLEN.W))
   val crevoke = Output(UInt(XLEN.W))
   val fu_data_cur  = Input(new fu_data_t)
   val rd_result_o  = Output(new cap_result_t )
     
  })
  //  val fu_data_cur  = Wire(new fu_data_t)
  //  val rd_result_o  = Wire(new cap_result_t )

  //  val fu_data_cur  = Module(new fu_data_t)
  //  val rd_result_o  = Module(new cap_result_t )

  //  val fu_data_cur  = IO(Input(new fu_data_t))
  //  val rd_result_o  = IO(Output(new cap_result_t ))
   val rs1_cc=new cap_cc_t
   val rs1_c =new cap_fat_t
   val cap_uncompress_cap=new cap_uncompress
   val cap_compress_cap  =new cap_compress


   rs1_cc.revnode_id := io.fu_data_cur.cap_a(0,30)//31

Error:

Exception in thread "main" chisel3.package$ExpectedChiselTypeException: 'UInt<1>(0)' must be a Chisel type, not hardware

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