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John T.
John T.

Reputation: 1

Automatically add hierarchies in Verilog code

I have a working code generator, that on top-level, just instantiates modules and takes care of all the connectivty - that one is proven to be working.

I would like now to partition some of the instances into a seperate module, basically adding a hierarchy to the generated code. The top-level should now instantiate the new module (with the internal instantiation) and hook up the new signals. The module also needs to be generated automatically.

The question to me is now how to design that. On the one hand, I already have a working code generator but it needs changes.

  1. Rewrite the code generator to support partitions/hierarchies
  2. Perform a post-process step, that introduces the hierarchies

I am not sure if the second approach could be implemenented by parsing the generated RTL code into an AST, introduce the new hierarchy there, and then re-generate the RTL code.

Of couse, I am open for other design decisisons as well.

Upvotes: -1

Views: 146

Answers (1)

Mikef
Mikef

Reputation: 2508

Consider simplifying your work by the use of SystemVerilog's .* notation see systemverilog-what-does-dot-star-mean for the instances rather than elaborating each port on instance mappings. Its not as risky as it seems, using .* invokes tighter type checking from the tools.

One factor in the consideration is synthesis support. You might want to try a hand-created, toy sized design in the tools you intend to use for synthesis to determine the limits of support. You may find that it works fine for simple data types (vectors aka packed variables) but has trouble for more interesting types. Or, you may find that it works great in vendor A but not as well in vendor X or the other way around, or something else.

Upvotes: 0

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