CODEWITHSUNDEEP
computer-scienceinterruptvirtualizationinstruction-set
Jacob Miller
Jacob Miller

Reputation: 37

What does "trap entry point" means?

From Chapter 2 (The Popek/Goldberg Theorem) in Hardware and Software Support for Virtualization - Synthesis Lectures on Computer Architecture,

... consider what an operating system for such an architecture would look like (in the absence of a VMM).

The kernel would run in supervisor mode (M = s), and applications would always run in user mode (M = u).

During initialization, the kernel first sets the trap entry point: MEM[0] (M:s,B:0,L:SZ,PC:trap_en).

The kernel would allocate a contiguous range of physical memory for each application.

To launch or resume an application stored in physical memory at [B,B+L[ and currently executing instruction P C, the operating system would simply load PSW (M:u,L,C,PC).

At the trap entry point (P C =trap_en), the kernel would first decode the instruction stored at MEM1.PC to determine the cause of the trap, and then take appropriate action.

Although idealized, notably because of the lack of registers, this architectural model is not fundamentally different from the ones that we are all familiar with today. ...

What does "trap entry point" mentioned above mean in the context? Does it mean the address of the memory location where the old PSW is saved when a trap occurs as stated in the original Popek and Goldberg paper where MEM[0] or E[0] is used for that purpose?

The Popek and Goldberg paper has this description of the traps:

Traps

We continue with the model of the third generation machine by defining the action of a trap. An instruction i is said to trap if i(E1,M1,P1,R1) = (E2,M2,P2,R2) where

E2[j] = E1[j], for0 <j < q,

E2[0] = (M1,P1,R1)

(M2, P2, R2) = E11.

Hence, when an instruction traps, storage is left unchanged, except for location zero in which is put the PSW that was in effect just before the instruction trapped. The PSW to be in effect after the instruction trapped is taken from location one. In the software of most third generation machines, one expects that M2 = s and R2 = (0,q-1).

Intuitively, a trap automatically saves the current state of the machine and passes control of a prespecified routine by changing the processor mode, the relocation bounds register, and the program counter to the values specified in E11. Our definition could be relaxed to include cases in which the trap does not block the instruction but rather gains control immediately afterward or even some number of instructions later, providing that the state of the machine is stored in such a way as to be reversible to the point at which the instruction causing the trap was about to be executed.

(Note that nomentclature is bit different between the two texts.)

Upvotes: -1

Views: 100

Answers (1)

Stephen C
Stephen C

Reputation: 719376

The trap entry point is the memory address that you branch to when a trap occurs.

Does it mean the address of the memory location where the old PSW is saved when a trap occurs

No. It is the value that is loaded into the PC when the trap occurs.

(I'm not going to give you a citations taken from the sources you are using. The above just explains this from the perspective of real hardware ... on the assumption that Popek & Goldberg's model is intended to be based on how real hardware behaves.)

Upvotes: 3

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