CODEWITHSUNDEEP
concatenationverilog
tech_scholar
tech_scholar

Reputation: 35

How to concatenate number (1'b1) and `define in a single statement

I am writing a test bench in which I am trying to define a bit stream like so:

`define PREAMBLE (10'b1010101011)
`define FUNC_ENERGY (4'b0001)

reg bit_stream_tb = {`PREAMBLE, `FUNC_ENERGY, 1'b1};

Once I display the bit_stream_tb in my initial statement, I only get a '1'.

$display("bit_stream: ", bit_stream_tb);

Output:

bit_stream: 1

How do I concatenate it so that the output is:

bit_stream: 1010101011     0001          1
            PREAMBLE     FUNC_ENERGY

without the whitespaces of course.

In later stages of my program I want to be able to "spam" a series of `DEFINES to get a bit stream. I thought the easiest way is to just concatenate into a reg, this doesn't work as intended.

I do not want to have a long `DEFINE like so:

`DEFINE `PREAMBLE `FUNC_ENERGY 1,

because it is not as modular as I like.

Upvotes: 1

Views: 34

Answers (1)

toolic
toolic

Reputation: 62236

The output only shows 1 because you declared bit_stream_tb as a 1-bit signal and it is only being assigned the LSB of the concatenation, namely 1'b1.

This declaration creates a 1-bit signal because there is no range specifier:

reg bit_stream_tb

You should use a range which specifies a 15-bit signal like this:

reg [14:0] bit_stream_tb = {`PREAMBLE, `FUNC_ENERGY, 1'b1};

Here is a complete code example:

module tb;

`define PREAMBLE (10'b1010101011)
`define FUNC_ENERGY (4'b0001)

reg [14:0] bit_stream_tb = {`PREAMBLE, `FUNC_ENERGY, 1'b1};

initial begin
    $display("bit_stream: ", bit_stream_tb);
end

endmodule

Output:

bit_stream: 21859

To display in binary format:

$display("bit_stream: %b", bit_stream_tb);

Output:

bit_stream: 101010101100011

If you want to display the numbers separately, you should not concatenate them:

$display("bit_stream: %b %b %b", `PREAMBLE, `FUNC_ENERGY, 1'b1);

Output:

bit_stream: 1010101011 0001 1

Upvotes: 1

Related Questions