CODEWITHSUNDEEP
vhdl
joethecoder
joethecoder

Reputation: 175

Results settling in VHDL in a 4-Bit MIPS ALU?

Considering the first question went so well, still need a little help though, again its for a practice exam and I have the answers, just need the reasoning and thought process, Thanks guys.

Consider a 4-bit version of MIPS ALU shown on the next page. Here add/subt determines whether an addition (add/subt = 0) or subtraction (add/subt = 1) takes place and op selects the multiplexor output (assume that the top input is selected by an op of 000, etc.). Assume that it takes

2 ticks for a 2-input and, or, xor, nor to settle at its final output

4 ticks for a 4-input nor to settle at its final output

6 ticks for a 6-input multiplexor to settle at its final output

8 ticks from the latest arriving input for the sum and carry outputs of a 1-bit full adder to settle at their final output

When do the result outputs settle at their final values for the inputs shown below (ignoring the test for zero and for overflow)?

add/subt = 0        outputs settle at ?
op = 000
A = 1111
B = 0001

http://img600.imageshack.us/img600/797/cmpen331diagram.png

Upvotes: 0

Views: 439

Answers (1)

Paul Seeb
Paul Seeb

Reputation: 6156

Go through the diagram and write delta numbers for each element as it gets its signal.

For the whole adder

LSB block

time through 5 (2-input AND, OR, XOR) is 2 ticks. The adder needs 8 ticks to propegate so its output isn't ready until 10 total ticks after start. The mux (now with all inputs updated) takes 6 ticks to process meaning the LSB adding circuit takes 16 ticks total before propagating completely the first time.

LSB + 1 block

The second adder needs the carry bit from the first adder so it needs to wait 10 total ticks before it can start adding the correct values. It outputs at 18 total ticks into the mux which is completed at 24 total ticks.

LSB + 2 block

the third adder needs the carry bit from the second adder so it needs to wait 20 total ticks before it can start adding the correct values. It outputs at 28 total ticks into the mux which is completed at 34 total ticks.

MSB block

the third adder needs the carry bit from the third adder so it needs to wait 30 total ticks before it can start adding the correct values. It outputs at 38 total ticks into the mux which is completed at 44 total ticks.

set bit

not positive what this is for but its signal doesnt get into the mux in the LSB block until 40 ticks after start. Going through the mux in the LSB block takes 6 ticks therefore 46 ticks later the final signal has finished propagating from the LSB block to result0 and has entered the 4-bit nor so the entire adder settles at 46 ticks WORST CASE

The test for zero brings the final tick count to 50

The overflow is ready at 44 total ticks

The numbers we are given offer a worst case (all carry bits for all blocks are needed).

Upvotes: 1

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