CODEWITHSUNDEEP
xilinx
Abu Bakar
Abu Bakar

Reputation: 185

Xilinx ISE build time and already compiled modules

Is there a way to speed up Xilinx ISE build process? I have multiple verilog HDL files in my project. Sometimes I implement a minor change in at a place in one file. However the build time is same as if the whole project were changed. I think software does not offer any advantage for already build modules.

I know its hardware, but is there some way out. I am really trouble with my slow progress. Any other tips to make the process will be appreciated.

Yours Truely

Abu Bakar

Upvotes: 2

Views: 2619

Answers (2)

OutputLogic
OutputLogic

Reputation: 796

There are quite a few things you can do to speed up an FPGA build. Among them:
- floorplanning
- design partitioning (Xilinx and Altera have some differences)
- adding false paths and mulitcycle paths constraints
- playing with synthesis and physical implementation tool options
- choice of the reset scheme can also affect the build time
- not over-constraining timing

I discuss this very topic in more detail in my book.

Thanks.

Upvotes: 1

Martin Thompson
Martin Thompson

Reputation: 16812

You can partition the design to help speed up the place and route process in a large design. But to be honest, FPGA builds are always going to be pretty lengthy :(

That's why most of us start out doing builds and debugging on the bench and very quickly move to debugging the code in a simulator (which is very fast to compile - seconds), and only when it works there doing the loooong build for silicon (hours).

Upvotes: 0

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