CODEWITHSUNDEEP
fpgaxilinx-ise
Reflection
Reflection

Reputation: 397

force ISE synthesis tool to synthesize a signal

In Xilinx ISE (using VHDL language), I have defined these signals:

signal  counter  : integer range 0 to 24_000_000;
signal  chTriger : std_logic :='0';

and have written the following code:

process_counter: process(clk)
begin 
  if ( clk'event and clk = '1') then
    if (counter < 8192) then
        counter  <= counter + 1;
        chTriger <= not chTriger;
    end if;
  end if;
end process process_counter;`

In ChipScope's select net menu, there is neither a counter nor chTriger signal due to optimization.
How can I force ISE synthesis tool to synthesize a signal?

Upvotes: 1

Views: 182

Answers (2)

Oldfart
Oldfart

Reputation: 6269

Read through the Xilinx constraints guide here especially the synthesis constraints. There is one which is called "KEEP".

In general it is a very useful document to browse if only so you have an idea what you can (and can't do).

Upvotes: 3

Rodney
Rodney

Reputation: 3061

Output chTriger to an external pin on the FPGA. Then it can't be optimized away.

And since chTriger depends on counter, then counter won't be optimized away either.

Upvotes: 0

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