Reputation: 6623
I'm programming in VHDL and trying to configure an LCD. My questions are related to the LCD-interface-timing and the times required for Power-On-Initilization.
When doing the initialization, there are some timing restrictions for example in the user guide says something like:
When I write the 0x30 to the LCD should I respect the 240ns + the times on interface-timing? (those for setup, enable high, enable hold, enable low).
Correct me if I'm wrong, but what I think is when I'm at initialization I don't care about interface-timing. When I'm sending commands (like function set, display On/Off, so on) I will take care of interface-timing.
Thanks. !
Upvotes: 0
Views: 1172
Reputation: 6146
New Answer:
Following the datasheet provided in comments http://www.xilinx.com/support/documentation/boards_and_kits/ug334.pdf
Worth noting that most of your comments claim that the interface timing is longer then the setup timing. This is Backwards. It takes longer to set up than to talk with the LCD.
To make this easier for me I'm going to make a pseudo function call called pulse LCD_E that you can replace in your head each time.
Definition of pulse LCD_E
wait a minimum of 40 ns (2 clock cycles at 50 MHz)
set LCD_E high
wait a minimum of 230 ns (12 clock cycles at 50 MHz)
set LCD_E low
wait a minium 10 ns before changes (.5 clock cycle)
The timing diagram for the standard write command asks you to
set LCD_RS, LCD_DB(7:4), LCD_RW
pulse LCD_E
reset LCD_RS, LCD_DB(7:4), LCD_RW for lower nibble
wait 1 us
pulse LCD_E
wait a minium of 40 us before repeating
The initialization is VERY similar although you have an initial wait time and are only writing the 4 bit commands with longer waits in between.
Do this for initialization
wait at least 15 ms (750,000 clock cycles at 50 MHz)
set LCD_DB<7:4> = 0x3
pulse LCD_E
wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
set LCD_DB<7:4> = 0x3,
pulse LCD_E
wait 100 μs or longer, which is 5,000 clock cycles at 50 MHz.
set LCD_DB<7:4> = 0x3
pulse LCD_E
wait 40 μs or longer, which is 2,000 clock cycles at 50 MHz.
set LCD_DB<7:4> = 0x2
pulse LCD_E
wait 40 μs or longer, which is 2,000 clock cycles at 50 MH
Initialization complete
If you need to eak out faster write times for some reason you can set the next data input during the longer waits and remove the initial wait in pulse LCD_E
In defense of my old answer. From the datasheet~~
After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient
eight-bit PicoBlaze embedded controller. After initialization, the PicoBlaze controller is
available for more complex control or computation beyond simply driving the display.
Old answer:
If this is going on an FPGA and you have other timing constraints (like wait times) you might consider using this
http://en.wikipedia.org/wiki/PicoBlaze
It is a VHDL implementation of an 8 bit micro controller, very useful for setting up, writing, and reading information from an LCD. The chip set is very simple and easy to pick up. Plus you get to code your own peripherals :)
Its free software and I think you can download it all here. It comes with its own IDE, and debugger.
http://www.picoblaze.info/tools.html
If its just for a small project you might just want to do all the coding yourself for delays. But if its going in a larger project this is pretty useful and its worth learning. I think it runs on a 50 MHz clock max so you might need to do some digital clock management if you are using a faster clock.
Upvotes: 1
Reputation: 3365
You always need to respect the interface timings when writing anything to the display controller or you could send invalid data. The longer timeouts are typically to give the display controller time to run various software routines which may prevent it from monitoring the interface port.
So, yes, you need to respect the interface timings when writing the 0x30 as part of the initialization sequence.
Upvotes: 1