CODEWITHSUNDEEP
cachinghardwarecpu-architecture
Pwn
Pwn

Reputation: 3455

L1/2 cache problem

could L1/L2 cache line each cache multiple copies of the main memory data word?

Upvotes: 1

Views: 707

Answers (4)

sybreon
sybreon

Reputation: 3156

Yes it can. L1 copy is updated but has not been flushed to L2. This happens only if L1 and L2 are non-exclusive caches. This is obvious for uni-processors but it is even more so for multi-processors which typically have their own L1 caches for each core.

It all depends on the cache architecture - whether it guarantees any sort of thing.

Upvotes: 0

Ben Schwehn
Ben Schwehn

Reputation: 4575

It's possible that the main memory is in a cache more than once. Obviously that's true and a common occurrence for multiprocessor machines. But even on uni processor machines, it can happen.

Consider a Pentium CPU that has a split L1 instruction/data cache. Instructions only go to the I-cache, data only to the D-cache. Now if the OS allows self modifying code, the same memory could be loaded into both the I- and D-cache, once as data, once as instructions. Now you have that data twice in the L1 cache. Therefore a CPU with such a split cache architecture must employ a cache coherence protocol to avoid race conditions/corruption.

Upvotes: 1

Massimiliano
Massimiliano

Reputation: 17000

Every cache basically stores some small subset of the whole memory. When CPU needs a word from memory it first goes to L1, then to L2 cache and so on, before the main memory is checked. So a particular memory word can be in L2 and in L1 simultaneously, but it can't be stored two times in L1, because that is not necessary.

Upvotes: 0

pjc50
pjc50

Reputation: 1755

No - if it's already in the cache the MMU will use that rather than creating another copy.

Upvotes: 0

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