CODEWITHSUNDEEP
vhdlfpga
tonionio
tonionio

Reputation: 13

FIFO control signals and extraction of bits for routing logic

I am currently building a network-on-chip router in VHDL in order to implement a 64-core 2-D MESH network on an FPGA.Each core has its own router and each router has 5 ports (north , south , west , east ,local port for communication with the processing unit) Each one of the ports have an input FIFO and an OUTPUT FIFO . So the input FIFO communicates with the outpuf fifo of the next destination router and the output fifo of this port with the input fifo of the source router.

My problem is that I am not using a Finite state machine to control the FIFOS write/read_eneable and FIFO_FULL FIFO_EMPTY signals and I do not know where these signals must be used in order to get the router working.

My FIFO is generated by xilinx CORE Generator and its a synchronous FIFO with the following signals : Input : Clock , Data in , read_enable , write_enable . Outputs : Data_out , fifo_full , fifo_empty , First 6 bits of the packet . This last output is used in order to get out of the fifo the first 6 bits of the packet in order to be used for routing decision by the XY routing block.

So my problem is that I cannot understand how to control the write/read_enable and fifo_full/empty of the FIFO and in addition how to extract the 6 bits in order to send them to the routing block.

Thank you in advance.

P.s. If anything is not clear please ask me to give further details.

_______________ANSWER REPLY ___________________

Hello there simon!!I really appreciate the time spend to give your answer.

Basically I am going to have packets of 32bytes to process. So I must find a way to devide the packet into flits and then as the flits enter the FIFO the first 6 bits will be used for routing. This way I can simulate random traffic.

An example to give you to understand. A 16-core mesh network has the following coordinates: 30 31 32 33 20 21 22 23 10 11 12 13 00 01 02 03

So imagine that each one of these 2bit number represent a router. In this case we need 4 bits not 6. So as the 4 bits enter the XY routing block. the first 2 bits are compared with the first bit of the coordinate and the second 2 bits are compared with the second bit of the coordinate.

So if we want to go from router 00 to router 22 the data coming into router 00 will have to be oriented to the correct output of this router. So if the destination is 22 then we have X-axis routing first so the flits will exit the east port and move until they reach router 02 and then they will be router to the Y-axis to head up to router 22.

I hope you can understand what I am saying!

If not please let me know!

With regards

Upvotes: 1

Views: 1893

Answers (1)

simon
simon

Reputation: 1145

  • Controlling an input FIFO: Use the full signal of that input FIFO and the empty signal of the corresponding output FIFO to generate the write enable signal (condition: write when the input FIFO is not full and the output FIFO is not empty, i.e. new data is available and can be written)
  • Controlling an output FIFO: Use the read enable signal of the corresponding input FIFO as write enable (if data was read it must be removed from the output FIFO to avoid being read multiple times by the input FIFO)

I don't understand what you're doing with the 6 bits you mention. Is this the address of the input FIFO where the data item of the output FIFO should be written to? If you clarify I can update my reply.

Upvotes: 2

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