CODEWITHSUNDEEP
cpu-architectureinstruction-set
nullpotent
nullpotent

Reputation: 9260

CISC instruction length

I was wondering, what is the maximum possible length of a CISC instruction on most of today's CISC architectures?

I haven't found the definitive answer yet, but it is suggested that it's 16 bytes long, in theory.

In the video @ around 15:00 mins, why does the speaker suggests "in theory" and why exactly 16 bytes?

Upvotes: 2

Views: 1250

Answers (2)

phuclv
phuclv

Reputation: 42032

CISC is a design philosophy, not an architecture, therefore there's no such thing as "CISC instruction length", only instruction length of a specific CISC architecture (like x86 or Motorola 68k)

Talking specifically about x86 then the limit is 15 bytes. Theoretically the instruction length can be infinite because prefixes can be repeated. However that makes it difficult for the decoder so in 80286 Intel began to limit it to 10 bytes, and then 15 bytes in later ISA versions. For more information about it read

Also note that RISC doesn't mean fixed-length instructions. Modern MIPS, ARM, RISC-V... all have a variable length instruction mode to increase code density

Upvotes: 5

Bo Persson
Bo Persson

Reputation: 92381

In practice as well. For the x86-64 AMD has limited the allowed instruction length to 15 bytes. After that, the instruction decoder will give up and signal an error.

Otherwise, with multiple instruction prefixes and override bytes, we don't know exactly how long the instruction could get. No limit at all, if we allow redundant repetitions of some prefixes.

Agner Fog describes the problem:

Executing three, four or five instructions simultaneously is not unusual. The limit is not the execution units, which we have plenty of, but the instruction decoder. The length of an instruction can be anywhere from one to fifteen bytes. If we want to decode several instructions simultaneously, then we have a serious problem. We have to know the length of the first instruction before we know where the second instruction begins. So we can't decode the second instruction before we have decoded the first instruction. The decoding is a serial process by nature, and it takes a lot of hardware to be able to decode multiple instructions per clock cycle. In other words, the decoding of instructions can be a serious bottleneck, and it becomes worse the more complicated the instruction codes are.

See the rest of his blog post here.

Upvotes: 5

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