CODEWITHSUNDEEP
countervhdlclockfrequencyperiod
Triple777er
Triple777er

Reputation: 631

VHDL - determining counter period

Dear intellectual beings of SO,

I just wanted to clear some doubts I'm having about determining the time it takes to iterate through a complete loop. Consider I have a 50Mhz clock which means the clock period is 20 ns.

Now, if I have a counter that counts from 0 to 500, does this counter take 20ns x 500 = 10 us to complete the entire loop?

Thankyou.

Upvotes: 1

Views: 1471

Answers (1)

sonicwave
sonicwave

Reputation: 6092

Short answer: yes.

Long answer: In FPGAs you program hardware. The process statements you use run in parallel, and not sequentially as C/C++/etc. code does on a normal microprocessor.

Example:

signal sig_a : UNSIGNED(3 downto 0) := (others => '0');
signal sig_b : SIGNED(7 downto 0) := (others => '0');
signal sig_c : std_logic := '0';

process(clk)
begin
    if(rising_edge(clk)) then
        sig_a <= sig_a + 1;
        sig_b <= sig_b - 1;
        sig_c <= not sig_c;
    end if;
end process;

Whenever you get a clock signal (every 20ns with a 50 MHz clock), all three statements inside the process will be executed simultaneously. All three signals will be implemented in flip-flops, so when the propagation delay is over (consult your FPGA datasheet for the exact values for your device), all three signals will have their new value.

The process does thus not "wait" for the statements to be complete, but are rather "triggered" by the clock. This will happen on every single rising edge of the clock, so to execute the statements 500 times, you'll need 500 clock cycles = 10 us at 50 MHz.

Upvotes: 2

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