CODEWITHSUNDEEP
verilog
user1580096
user1580096

Reputation: 487

Why are output nets also required to be redeclared as either 'wire' or 'reg'?

Why do we have to take the same variable name of an output and also wire for getting the value? eg:

 module TEST(INP1,INP2,CIN,COUT,SUM);
 input [31:0] INP1;
 input [31:0] INP2;
 output [31:0] SUM;
 input CIN;
 output COUT;

 wire [31:0] SUM;// Again redefined 
 wire COUT; // Again Redefined
 assign {COUT,SUM} = INP1 + INP2 + CIN ;

Example for getting the Carry-out and the Sum of two numbers and Carry-In taken as the input.

Upvotes: 4

Views: 5004

Answers (3)

Morgan
Morgan

Reputation: 20514

Verilog 1995 did require the port direction to be listed after. Output wire types were implicit and regs could be declared inline with direction.

module TEST(A,B,C,D);
  input  [31:0] A;
  input  [31:0] B;
  output [31:0] C;
  output        D;

  reg D;

could be written as:

module TEST(A,B,C,D);
  input      [31:0] A;
  input      [31:0] B;
  output     [31:0] C;
  output reg        D; //Only declared twice

Since Verilog 2001 the extra definition is no longer required and they can be declared inline (ANSI-Style).

module TEST(
  input      [31:0] A,
  input      [31:0] B,
  output     [31:0] C,
  output reg        D  // Declared Once
);

From SystemVerilog (2009) we have the logic type, you no longer have to switch between reg and wire types. The only requirement is that if you need to tri-state use wire or tri. 

module TEST(
  input        [31:0] A,
  input        [31:0] B,
  output logic [31:0] C,
  output logic        D
);

My understanding of the original requirement for having reg and wire types was for simulation speed or ease of simulator design. The value of a wire is evaluated every simulation delta cycle while a reg is only evaluated when triggered by the sensitivity list.

Upvotes: 4

toolic
toolic

Reputation: 62037

It is not necessary to declare an output also as a wire. Furthermore, you can avoid duplicating the port list by using ANSI-stlye port declarations:

module TEST (
    input [31:0] INP1,
    input [31:0] INP2,
    output [31:0] SUM,
    input CIN,
    output COUT
);

    assign {COUT,SUM} = INP1 + INP2 + CIN ;
endmodule

In your example, you do not need to declare outputs as reg. But, if you need to for another circuit, you can declare the type on the same line, such as:

output reg [31:0] Q;

Upvotes: 4

Tim
Tim

Reputation: 35933

Because just declaring a net as output doesn't describe if it is a reg type or a wire type.

An output can either be driven by a wire or reg, you have to tell it what type the driver is going to be.

Upvotes: -1

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