CODEWITHSUNDEEP
verilog
Andy Shulman
Andy Shulman

Reputation: 1925

Having trouble with Verilog inout wires

For the record, I'm a complete Verilog newbie. I'm writing a module that uses a few bidirectional buses.

inout wire [KEY_SIZE-1:0] prevKey;
inout wire [TAG_SIZE-1:0] prevTag;

inout wire [KEY_SIZE-1:0] nextKey;
inout wire [TAG_SIZE-1:0] nextTag;

I know how I read things off of the bus, but how do I write something onto it? If I use an assign statement to a reg, will the value of the reg get clobbered when new data comes onto the wire? Is dealing with an inout port worth the hassle, or should I just make an input and and output bus for each?

Upvotes: 4

Views: 15076

Answers (1)

Tim
Tim

Reputation: 35943

If I use an assign statement to a reg...

This statement doesn't really make sense, you don't do assignments to regs, you do assignments to wires.

Simple example of driving an inout wire:

inout wire bidir_wire;

reg drive_value;
reg drive_enable;
reg something;

assign bidir_wire = drive_enable ? drive_value : 1'bz; 

always @(posedge clk) begin
    drive_value  <= ... ;  //assign a drive value based on some criteria
    drive_enable <= ...;
    something    <= bidir_wire; //do something with the input value
end

Upvotes: 6

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