Higher-order functions in VHDL or Verilog

Question

I've been programming in more functional-style languages and have gotten to appreciate things like tuples, and higher-order functions such as maps, and folds/aggregates. Do either VHDL or Verilog have any of these kinds of constructs?

For example, is there any way to do even simple things like

divByThreeCount = count (\x -> x `mod` 3 == 0) myArray

or

myArray2 = map (\x -> x `mod` 3) myArray

or even better yet let me define my own higher-level constructs recursively, in either of these languages?

Answer 1

BlueSpec is used by a small com. known by few people only - INTEL

It’s an extension of SystemVerilog (SV) and called BSV

But it’s NOT open - I don’t think you can try use or even learn it without paying BlueSpec.com BIG money

There’s also Lava that’s used by Xilinx but I don’t know if you can use it directly.

Note: In Vhdl functions (and maybe Verilog too) CAN’T have time delay (you can’t ask function to wait for clk event) Vhdl has a std. lib. for complex num. cal. But in Vhdl you can change or overload a system function like add (“+”) and define your implementation. You can declare vector or matrix add sub mul or div (+ - * /) function, use generic size (any) and recursive declarations - most synthesizers will "understand you" and do what you’ve asked.

Answer 2

Have a look at http://clash-lang.org for an example of a higher-order language that is transpiled into VHDL/Verilog. It allows functions to be passed as arguments, currying etc., even a limited set of recursive data structures (Vec). As you would expect the pure moore function instantiates a stateful Moore machine given step/output functions and a start state. It has this signature:

moore :: (s -> i -> s) -> (s -> o) -> s -> Signal i -> Signal o

Signals model the time-evolved values in sequential logic.

Answer 3

I think you're right that there is a clash between the imperative style of HDLs and the more functional aspects of combinatorial circuits. Describing parallel circuits with languages which are linear in nature is odd, but I think a full blown functional HDL would be a disaster.

The thing with functional languages (I find) is that it's very easy to write code which takes huge resources, either in time, memory, or processing power. That's their power; they can express complexity quite succinctly, but they do so at the expense of resource management. Put that in an HDL and I think you'll have a lot of large, power hungry designs when synthesised.

Take your map example:

myArray2 = map (\x -> x `mod` 3) myArray

How would you like that to synthesize? To me you've described a modulo operator per element of the array. Ignoring the fact that modulo isn't cheap, was that what you intended, and how would you change it if it wasn't? If I start breaking that function up in some way so that I can say "instantiate a single operator and use it multiple times" I lost a lot of the power of functional languages.

...and then we've got retained state. Retained state is everywhere in hardware. You need it. You certainly wouldn't use a purely functional language.

That said, don't throw away your functional design patterns. Combinatorial processes (VHDL) and "always blocks" (Verilog) can be viewed as functions that apply themselves to the data presented at their input. Pipelines can be viewed as chains of functions. Often the way you structure a design looks functional, and can share a lot with the "Actor" design pattern that's popular in Erlang.

So is there stuff to learn from functional programming? Certainly. Do I wish VHDL and Verilog took more from functional languages? Sometimes. The trouble is functional languages get too high level too quickly. If I can't distinguish between "use one instance of f() many times" and "use many instances of f()" then it doesn't do what a Hardware Description Language must do... describe hardware.