CODEWITHSUNDEEP
modelsim
henry
henry

Reputation: 185

macros defined in verilog file but error shows undifined macros in modelsim

I have defined the macros of all my verilog files in one verilog file, say FabScalarParam.v and I compile the FabScalarParam.v first in the system.do file then compile other verilog files.

But when I run "do system.do" to compile the design, it shows me the errors like this,

# ** Error: I:/programming/EDK/project_4/pcores/instruction_side_v1_00_a/hdl/verilog/StallUnit.v(6): (vlog-2163) Macro `MAX_STALL_CYCLES_LOG is undefined.

It says that some macros are not defined. Is there any method to choose the FabScalarParam.v as global file in compile list in modelsim? Due to the large number of macros, I cannot specify all the macros using the method: compile --> compile options --> verilog & system verilog --> other verilog options --> Macros.

I use modelsim 6.5, xilinx edk 12.4

Upvotes: 1

Views: 21417

Answers (5)

John
John

Reputation: 11

This is my work around without adding `include in every files needing macros

vlog -mfcu -y <path/to/source/files> +libext+.v+.sv <source file 1> <source file 2> <... source file N>

-mfcu let vlog treats all source files in one command line as one compilation unit. If macro are defined in <source file 1>, they are visible to all following source files after it.

Upvotes: 1

stephan
stephan

Reputation: 1

You can compile a verilog file and define the precompiler macro that will be applied for this file by adding the following option to vlog:

+define+<macro_name>[=<macro_text>]

which Same as compiler directive: `define macro_name macro_text

for example:

vlog +define+macro_name -work work project.v

Upvotes: 0

user3595996
user3595996

Reputation: 11

I had the same problem when I compiled my project with script.
At last, I figure out you can't compile your macro and verilog files in different scope.
EX: 

vlog -work work macro.v  
vlog -work work project.v

You have to: 

vlog -work work macro.v project.v

Compiling them in one vlog command can solve the problem.

Upvotes: 1

Greg
Greg

Reputation: 19104

This has to do with compile order. Compiler directives, which included macros are processed linearly by the compiler. See IEEE1364-2001 section 19 or IEEE1800-2009 section 22 for more detail. Make sure the macro file is the first file to that is compiled.

Manually adding the `include also works, however your compiler may give macro redefined warnings. It is recommend to encapsulate the macro definitions in a `ifdef/`ifndef. Doing so resolve the macro defined warnings. If multiple files refer to same `include then encapsulation of the macros may also improve compiler performance. See the following example.

macros.vh:

`ifndef macros_vh
// NOTE: for Verilog 1995 `ifndef is not supported use `ifdef macros_vh `else
`define macros_vh
/**************
* your macros *
* `define ... *
***************/
`endif

Then in your verilog files (*.v / *.sv)

`include "macro.vh"
/*************
 * your code *
 *************/

Upvotes: 2

henry
henry

Reputation: 185

I cannot find anything useful on Internet to set global file in the compile list in modelsim. So, I just manually add `include ... in each file to solve the problem. Though it is stupid, It works fine.

If someone knows how to set the global file in the compile list in modelsim, please update it. :-) Thanks.

Upvotes: 1

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