CODEWITHSUNDEEP
verilogdeclarationmodelsim
Rizwan Ali
Rizwan Ali

Reputation: 11

Verliog Modelsim Error 2388. already declared in this scope

This is my Verilog code below. I am getting 2 errors in Modelsim when I try to compile it.

** Error (suppressible): /home/ece4514/mul1.v(6): (vlog-2388) 'p' already declared in this scope (mul1). ** Error (suppressible): /home/ece4514/mul1.v(8): (vlog-2388) 'c' already declared in this scope (mul1).

module mul1(output [103:0] p, 
        output [51:0]  c, 
        input [51:0]   x,
        input [51:0]   y); 
reg [103:0]p;
reg [103:0]a;
reg c;
integer i; 

always @(x , y)
begin 
  a=x;
  p=0; // needs to zeroed
  for(i=0;i<104;i=i+1)
  begin
    if(y[i])
      p=p+a; // must be a blocking assignment
    a=a<<1;
  end

  for(i=103;i>=0;i=i-1)
  begin
    if (p[i])
        c=p[i:i-51];
        break;
    end

  end
endmodule

What change do I need to make?

Upvotes: 0

Views: 10289

Answers (1)

dave_59
dave_59

Reputation: 42698

You are mixing Verilog-1995 style port declarations, with Verilog-2001/SystemVerilog style. With the newer style, all the information about a port goes in the header.

module mul1(output reg [103:0] p, 
        output reg [51:0]  c, 
        input [51:0]   x,
        input [51:0]   y); 

reg [103:0]a;
integer i;

The older style had just the identifiers in the header, and you later declared the direction and type.

Upvotes: 1

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