CODEWITHSUNDEEP
vhdlunsignedsigned
Gabriel Lozano
Gabriel Lozano

Reputation: 41

VHDL std_logic_vector conversion to signed and unsigned with numeric_std

I have some doubts about the use of the conversions from std_logic_vector to signed/unsigned. I always use the conversion signed(...), unsigned(...), but when I try to use the conversions defined in the library numeric_std (to_signed, to unsigned), it doesn't work. Can someone explain to me why this happens? And why the conversion unsigned() and signed() works?

Upvotes: 4

Views: 65467

Answers (2)

vermaete
vermaete

Reputation: 1373

Because the std_logic_vector and signed/unsigned types are closely related, you can use the typecast way to convert. So signed(a_std_logic_vector) and unsigned(a_std_logic_vector) are okay. However, the functions to convert are also defined in the standard.

Take a look at the VHDL FAQ. This is an old website from the days that newsgroups were still hot, but it still has plenty of good information about VHDL.

Upvotes: 7

user1818839
user1818839

Reputation:

Look at the package spec for numeric_std. You will find that to_signed converts to signed ... from integer.

As "vermaete" says, signed is a closely related type to std_logic_vector so you don't need a conversion function there.

Upvotes: 2

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