CODEWITHSUNDEEP
type-conversionvhdl
user3056350
user3056350

Reputation: 67

VHDL writing std_logic_vector as a signed integer in file

I wonder how to write a std_logic_vector as a signed integer in VHDL testbench?

Upvotes: 1

Views: 3282

Answers (2)

Russell
Russell

Reputation: 3457

Using numeric_std:

signal test_in  : std_logic_vector(2 downto 0);
signal test_out : integer range -4 to 3;

test_out <= to_integer(signed(test_in));

Upvotes: 2

Martin Thompson
Martin Thompson

Reputation: 16802

You need to convert to an integer (using the use ieee.numeric_std.all;, which means you need to know if your std_logic_vector is representing a signed or unsigned number. Ideally, you'd use the relevant type rather than the bag-of-bits that std-logic_vector is.

Converting to an integer is as straightforward as:

int_variable := to_integer(some_vector);

If you must stick to a std_logic_vector you'll have to tell the compiler whether it is unsigned or signed like this:

int_variable := to_integer(unsigned(some_vector));

or this:

int_variable := to_integer(signed(some_vector));

Then you can write you integer to the file as you normally would.

Upvotes: 0

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