CODEWITHSUNDEEP
vhdlhdlmodelsim
JanBo
JanBo

Reputation: 2933

VHDL wait on multiple signal

signal a:bit:='1'; signal b:bit:='0'; signal c:bit:='0';
begin
  process
  variable d:bit:='0';
    begin
    if (a='1')or(b='0') then a <= inertial not d after 1ns;
  else a<=inertial not c after 1.5ns;
    end if;
    d := a and b;
  b <= inertial (b)nand(a or d) after 1ns;          
  wait on a,b,c;end process;
  c <= a and b after 1ns;
end Behavioral;

What happens if both a and b change their value at the same time, 2ns for ex.

Will the process trigger 2 times?

If it does, which values should be used for a,b, if we are going trough the process for the a event, is b signal changed at that time, or it will be changed when the process runs again for b?

Also the statement c <= a and b after 1ns; is outside of the process, how does it work with after? If there was no after, it would just be an AND unit, with no delay.

Upvotes: 2

Views: 2807

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16812

wait on a,b,c;

waits for one of the signal to have a transaction during a delta-cycle.

If it happens that two or all of them "activate", it makes no difference to the simulator, it will still just drop out of the wait. It won't "save up" the transactions from the current delta-cycle on the remaining signals and carry them forwards.

Upvotes: 2

user1818839
user1818839

Reputation:

I hope you understand this process will not synthesise correctly!

As for the process triggering once or twice, that will depend if the events on a or b occur in the same delta cycle. Add a Report statement to the process and find out.

Because the process drives A and B via delay statements, I expect both assignments to act in the same delta cycle; the first delta of the timestep so I expect it to be triggered once.

Now if you introduced a new signal "e" and drove it from the process instead of "b", and added the signal assignment b <= e; outside the process, you have introduced a delta cycle delay into "b", and the process should then wake up twice.

The statement c <= a and b after 1ns; is essentially a separate process sensitive to a and b, so it should work the same way.

You may find this answer helpful in understanding the delta cycle model.

Upvotes: 1

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