CODEWITHSUNDEEP
vhdl
olyc
olyc

Reputation: 29

VHDL for loop type error and shift error

I'm trying to write a for loop in VHDL, but I believe there is some type issue in the loop statement. I have a block that receives a 16-bit word, A, as input that indicates the number times I should shift another input, B. The output, C, shows the shifted version of B. My code looks like this:

TEMP_C := B;
FOR I IN 1 TO UNSIGNED(A) LOOP
  TEMP_C := TEMP_C(15) & TEMP_C(15 DOWNTO 1);
END LOOP;
C <= TEMP_C;

The compiler is complaining about the second line, and says "Range left bound type Integer is not the same as right bound type". Can someone explain to me why this line is wrong, and how do I fix it?

Upvotes: 1

Views: 1127

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16822

FOR I IN 1 TO to_integer(UNSIGNED(A)) LOOP

An unsigned vector is not the same as an integer. This is not Verilog!

Upvotes: 0

vermaete
vermaete

Reputation: 1373

On the left side you have '1', being an 'integer'. On the right side you have 'unsigned(std_logic_vector?)', being an 'unsigned'. An unsigned is still not the same as an 'integer'. An unsigned is still a collection of bits. Here for more info about 'unsigned'.

Anyhow this solution will help you more...

Upvotes: 1

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