CODEWITHSUNDEEP
vhdl
G.V.
G.V.

Reputation: 719

VHDL error in For loop

In the following code I receive the following errors, but I don't understand why is it an error.

library ieee;
use ieee.std_logic_1164.all;

entity RGSTR_SHFT_N_PARAL_B2 is

Generic (
     n: integer := 4  
     );

  port(
    DATA : in std_logic_vector((n-1) downto 0); 
    Shift_In : in std_logic; 
    Load : in std_logic;  
    Enable : in std_logic;  
CLK : in    std_logic;  
S : out   std_logic_vector((n-1) downto 0)   
        );
end entity RGSTR_SHFT_N_PARAL_B2;

architecture simple of RGSTR_SHFT_N_PARAL_B2 is

  signal temp_S: std_logic_vector((n-1) downto 0);

  signal LOW0, HIGH1: std_logic; -- Constant Signals   

  -- Use the D flip flop of B1 excersise
      component D_FF_B1 is
        port( 
        Enable      : in    std_logic;  
       Load        : in std_logic;  
    Load_Val    : in    std_logic;  
     Data_in     : in   std_logic;  
     CLK        : in    std_logic;  
     Q           : out   std_logic  
    );
  end component;

begin

  p0:process(Enable, CLK) is
  begin

-- Initialisations 

  LOW0  <= '0';
  HIGH1 <= '1';

    if (Enable = LOW0) then
           L0: for i in 0 to (n-1) loop
              temp_S(i) <= temp_S(i);
           end loop;
       elsif (CLK 'event and CLK = HIGH1) then 
           if (Load = LOW0)  then             -- Shifter is enabled
              L1: for i in 0 to (n-2) loop
                  temp_S(i) <= temp_S(i+1);
              end loop;
              temp_S(n-1) <= Shift_In;
           else                               -- Loader is enabled
              L2: for i in 0 to (n-1) loop
                X1: D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S(i));
              end loop;
           end if;
       end if;

  L3: for i in 0 to (n-1) loop
     S(i) <= temp_S(i);
  end loop;

  end process p0;

end architecture simple;

Error message:

Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text "port";  expecting "(", or "'", or "."
Error (10500): VHDL syntax error at RGSTR_SHFT_N_PARAL_B2.vhd(79) near text ";";  expecting ":=", or "<="

I compile the VHDL program with Quartus II.

Upvotes: 2

Views: 2689

Answers (1)

Morten Zilmer
Morten Zilmer

Reputation: 15934

Instantiation of a module in a process is not legal VHDL syntax, as seen in:

p0:process(Enable, CLK) is
begin
...
  L2: for i in 0 to (n-1) loop
    X1: D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S(i));
  end loop;
...
end process p0;

Instantiation of a module must be done as concurrent statement outside the process.

Based on the code, it looks like it may be possible to move the module instantiation outside the process with code that looks something like:

signal temp_S_x1 : std_logic_vector((n-1) downto 0);
...
L2 : for i in 0 to (n-1) generate
  X1 : D_FF_B1 port map(HIGH1, LOW0, LOW0, DATA(i), CLK, temp_S_x1(i));
end generate;
...
p0 : process(Enable, CLK) is
  ...
  L2: for i in 0 to (n-1) loop
    temp_S(n-1) <= temp_S_x1(i);
  end loop;

Note that you should declare the constants LOW0 and HIGH1 with constant instead of signal, and then remove the LOW0 and HIGH1 assign in p0 process:

constant LOW0 : std_logic := '0';
constant HIGH1 : std_logic := '1';

or simply use '0' and '1' directly instead of declaring any constants.

Also note that the p0 process is not a properly formated process for flip flops, so you will get some additional warnings from Quartus due to missing temp_S signal in sensitivity list. If Enable is use synchronously, then use a template like:

p0 : process(Enable, CLK) is
begin
  if rising_edge(CLK) then
    if (Enable = '0') then

Upvotes: 3

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