CODEWITHSUNDEEP
vhdlmodelsim
user2113607
user2113607

Reputation: 31

VHDL infinite loop

I'm writing a small piece of code to take a 32 bit input and output 2 bits at a time. I believe I'm having infinite loop problems from the while loop, based on simulation attempts. Everything looks right to me, compared to other examples of loops I've looked at. Any clue what I could be doing wrong?

library ieee;
use ieee.std_logic_1164.all;

entity regA is 
port(mpcnd: in std_logic_vector(31 downto 0);
      clk: in std_logic;
      twobits: out std_logic_vector(1 downto 0));
end regA;

architecture behavior of regA is 
begin
process
variable count: integer;
begin
count := 0;
while (count < 32) loop
    if rising_edge(clk) then
    twobits(0) <= mpcnd(count);
    twobits(1) <= mpcnd(count+1);
    count := count + 2;
    end if;
end loop;
end process;
end behavior;

Upvotes: 1

Views: 6758

Answers (1)

baldyHDL
baldyHDL

Reputation: 1387

for a process you need either a sensitivity list or a wait statement within. a (not synthesisable but simulatable) version of your process could look as follows:

process
    variable count: integer;
begin
    count := 0;
    while (count < 32) loop
    wait until rising_edge(clk);-- if rising_edge(clk) then
    twobits(0) <= mpcnd(count);
    twobits(1) <= mpcnd(count+1);
    count := count + 2;
--end if;
end loop;
end process;

Upvotes: 2

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