CODEWITHSUNDEEP
vhdlmodelsim
nasim zeynali
nasim zeynali

Reputation: 3

near "loop": expecting IF; near "process": expecting LOOP

This is the error

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_signed.all;

use IEEE.numeric_std.all;

entity MULT is

GENERIC(n:integer:=4);

 port(A,B: in  std_logic_vector(n-1 downto 0);
       P : out std_logic_vector(2*n-1 downto 0)); -- PRODUCT

end entity;


architecture BOOTH of MULT is

begin

BOOTH:process(A,B)

 variable X:std_logic_vector(2*n downto 0); 

 variable Y:std_logic_vector(n-1 downto 0); 

 variable Z:std_logic_vector(n-1 downto 0); 

 variable U:std_logic_vector(n-1 downto 0); 

begin

for J in 0 to n-1 loop

 U(j):='0';

end loop;

 X:=U & A & '0';

 Y:=B;               
 
for I in 0 to n-1 loop

 if(X(1)='1' and X(0)='0') then

  Z:=X(2*n downto n+1);

   X(2*n downto n+1):= Z-Y;

    X(2*n-1 downto 0):=X(2*n downto 1);


 else if(X(1)='0' and X(0)='1') then

  Z:=X(2*n downto n+1);

   X(2*n downto n+1):= Z+Y;

    x(2*n-1 downto 0):=X(2*n downto 1);


 else

  X(2*n-1 downto 0):=X(2*n downto 1);

end if;

end loop;

P(2*n-1 downto 0) <= X(2*n downto 1);


end process;

end architecture BOOTH;

Upvotes: 0

Views: 507

Answers (1)

CherryDT
CherryDT

Reputation: 29011

Let's try to understand what the compiler is telling you here. At the end loop it was expecting an end if. That means that you are actually inside another if when you try to close your loop. The next error is just a consequence of the first.

Why is that so?

Let's check where the starts of the blocks in question could possibly be. At the end if above the end loop, you are obviously closing one if successfully, yet you are still inside another one, according to the compiler. You think you close the if(X(1)='1' and X(0)='0') then, but obviously you don't, otherwise we wouldn't have that error.

Is there another if between that one and the end if? Yes! It is in this line: else if(X(1)='0' and X(0)='1') then.

You obviously thought that this counts as part of the original if, but the compiler thinks otherwise, so that's the point where you would google else if vhdl. You would then find that the correct syntax is actually elsif, because otherwise you do else plus a new, separate if inside of the else, which is what happened here.

To visualize what happened, by using the indentation that would match what the compiler sees right now:

for I in 0 to n-1 loop
 if(X(1)='1' and X(0)='0') then
   ...
 else
   if(X(1)='0' and X(0)='1') then
    ...
   else
    ...
   end if;
 ??? (end if missing here)
end loop; <<< error, end if expected, end loop found

With elsif, it would be like this instead:

for I in 0 to n-1 loop
 if(X(1)='1' and X(0)='0') then
   ...
 elsif(X(1)='0' and X(0)='1') then
  ...
 else
  ...
 end if;
end loop;

Bottom line: You need elsif instead of else if.

By the way: Your indentation makes no sense. You have subsequent lines always indented one space further, even though they are on the same block level. This is only going to confuse you. Make sure you indent your code properly - there are also editor plugins out there that can help you with that.

Upvotes: 2

Related Questions