CODEWITHSUNDEEP
verilogfpga
Manish
Manish

Reputation: 543

Verilog changing a value of a variable

I am implementing a simple counter which is counting the number of time push buttons are pressed. I wrote the following code:

module lock(
anodes,cathodes,leds,
sw,btns,clk );

//input declarations
input[7:0] sw;
input[3:0]btns;
input clk;


always @(curbtns)
begin
if( prevbtns!=0 && curbtns==0)
begin
    counter_next = counter + 5'b00001;
end
else
    counter_next = counter;
prevbtns = curbtns;
end


always @(btns or sw)
begin
case(btns)
4'b0001:curbtns=4'b0001;
4'b0010:curbtns=4'b0010;
4'b0100:curbtns=4'b0100;
4'b1000:curbtns=4'b1000;
4'b0000:curbtns=4'b0000;
default:curbtns = prevbtns; 
endcase
end

always @(posedge clk)
begin
counter <=counter_next;
create_slow_clock(clk,slow_clock);
end
endmodule

When I simulate the above code in icraus verilog it seems to be working but on actual FPGA my counter is not changing. Is there any problem in the logic of incrementing the variable.

Updated code(Working)

always @(curbtns or prevbtns or counter)
begin
 if( prevbtns!=0 && curbtns==0)
 begin
 counter_next = counter + 5'b00001;
 end
 else
 counter_next = counter;
end

always @(posedge clk)
begin
counter <=counter_next;
prevbtns <=curbtns;
create_slow_clock(clk,slow_clock);
end

Upvotes: 1

Views: 5588

Answers (1)

Tim
Tim

Reputation: 35943

You look to be missing some signals in your sensitivity lists for the combinational always blocks.

For your code to be properly synthesizable, a combinational block must be sensitive to every input signal.

The first always block always @(curbtns) needs to be sensitive to prevbtns, curbtns, and counter.

The second block always @(btns or sw) also needs to be sensitive to prevbtns (I don't see sw used in this block anyway, should get rid of it).

I recommend changing both blocks to always @*, so that the lists may be automatically inferred, and it's not a fragile point of breakage if you change the logic and forget to change the list.

Upvotes: 1

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