CODEWITHSUNDEEP
vhdl
user2280448
user2280448

Reputation: 23

cyclically 8 bit shifter ,VHDL

I have the following problem: I have to implement 8 bit left shifter that makes one shift to left, the code of it is:

entity left_shift is

generic ( N: integer := 8);

Port(
    Databitsin : in STD_LOGIC_vector(N-1 downto 0);
    Databitsout : out STD_LOGIC_vector(N-1 downto 0);
    Carry: out std_logic  
);

end left_shift;

architecture Behavioral_l of left_shift is
begin
    Databitsout(N-1 downto 1)<= Databitsin(N-2 downto 0);
    Carry<=Databitsin(N-1);
end Behavioral_l;

then i have to implement another one that has to make one shift to the right

entity Right_shift is
generic ( N: integer := 8);
Port(
    Databitsin : in STD_LOGIC_vector(N-1 downto 0);
    Databitsout : out STD_LOGIC_vector(N-1 downto 0);
    Carry: out std_logic 
);

end Right_shift;

architecture Behavioral of Right_shift is
begin
    Databitsout(N-2 downto 0)<= Databitsin(N-1 downto 1);
    Carry<=Databitsin(0);
end Behavioral;

Now, I have to build a main Module which has to use these 2 components to make cyclically shift (left,right). How can I do that?

Upvotes: 0

Views: 2429

Answers (2)

baldyHDL
baldyHDL

Reputation: 1387

there's different ways to implement cyclical shift (=rotate!). if you add a direction-selector Dir, you can have both directions within one code.

ex.1

add "use IEEE.NUMERIC_STD.all" to make use of numeric_std package functions:

Databitsout<=std_logic_vector(rotate_right(unsigned(Databitsin),1)) when Dir='0' else
             std_logic_vector(rotate_left(unsigned(Databitsin),1));

ex. 2

use std_logic_vectors directly:

Databitsout<=Databitsin(0) & Databitsin(N-1 downto 1) when Dir='0' else
             Databitsin(N-2 downto 0) & Databitsin(N-1);

carry flag is the same in both:

Carry<=      Databitsin(0) when Dir='0' else 
             Databitsin(N-1);

Upvotes: 1

OllieB
OllieB

Reputation: 1431

This sounds a lot like homework, but never-the-less:

Firstly, why do you have to use two components? The elegant solution is to write one component capable of shifting left or right.

If you have some astoundingly good reason to do things the way you've suggested, try instantiating both and multiplexing between the databitsout signals of both depending on the desired diection. To make a cyclic shift instead of a linear one, you need to concatinate the carry bit into the appropriate end of the logic vector array.

Upvotes: 1

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