CODEWITHSUNDEEP
algorithmbit-manipulationconcatenationvhdlbit-shift
Develobeer
Develobeer

Reputation: 435

VHDL - Shift operation of N times with concatenation

I would like to know how can I do a shift operation in VHDL if I have 2 inputs, one input, DATA1 is a number (std_logic_vector), and the second input DATA2 represents the number of times I want to shift the first input. For example, if I must shift left always only one time, the code is

OUTALU <= '0' & DATA1(N-1 downto 1);

If I would like to shift DATA2 times, is it right writing:

for i in 0 to DATA2 loop
  OUTALU <= '0' & DATA1(N-1 downto 1);
  DATA1 <= OUTALU
end loop;

is it right? I must define signals and assign to these signals DATA1 and DATA2? Thank you for help

Upvotes: 2

Views: 2767

Answers (2)

Nicolas Roudel
Nicolas Roudel

Reputation: 91

datao <= std_logic_vector(unsigned(data1) sll to_integer(unsigned(data2)));

sll is shift left logical, filled with ‘0’

you can also use sla (shift left arithmetic, filled with right bit) instead sll.

ps: datao <= '0' & data1(7 downto 1) is a right shifter, not left :). use srl or sra.

Upvotes: 0

Jonathan Drolet
Jonathan Drolet

Reputation: 3388

What you seek is a barrel-shifter. You can do that like this:

OUTALU <= std_logic_vector(shift_left(unsigned(DATA1),  to_integer(unsigned(DATA2)))); -- Shift left
OUTALU <= std_logic_vector(shift_left(unsigned(DATA1),  to_integer(unsigned(DATA2)))); -- Shift right
OUTALU <= std_logic_vector(shift_left(  signed(DATA1),  to_integer(unsigned(DATA2)))); -- Arithmetic shift left
OUTALU <= std_logic_vector(shift_left(  signed(DATA1),  to_integer(unsigned(DATA2)))); -- Arithmetic shift right

This implies you use ieee.numeric_std.all' and thatDATA1andDATA2` are std_logic_vector, thus the casts.

Upvotes: 2

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