CODEWITHSUNDEEP
memorycomputer-sciencecpu-usagecpu-architecture
siddstuff
siddstuff

Reputation: 1255

Hit and miss ration in cache and average time calculation

I'm trying to solve a objective type question , came In examination. I actually don't know the right answer, and don't know how to get it , need your help. Thank you .

Question : In a certain system the main memory access time is 100 ns. The cache is 10 time faster than the main memory and uses the write though protocol. If the hit ratio for read request is 0.92 and 85% of the memory requests generated by the CPU are for read, the remaining being for write; then the average time consideration both read and write requests is

a) 14.62ns

b) 348.47ns

c) 29.62ns

d) 296.2ns

My work ::::

Well, memory access time = 100ns

cache access time would be = 10 ns (10 time faster)

In order to find avg time we have a formula

Tavg = hc+(1-h)M

   where h = hit rate
     (1-h) = miss rate
       c   = time to access information from cache
        M  = miss penalty  (time to access main memory)

Write through operation : cache location and main memory location is updated simultaneously.

It is given that 85% request generated by CPU is read request and 15% is write request.

Tavg = 0.85(avg time for read request)+ 0.15(avg time for write request)
     = 0.85(0.92*10+0.08*100)+0.15(avg time for write request)

//* 0.92 is a hit ratio for read request , but hit ratio for write request is not given ??

If I assume that hit hit ratio for write request is same as hit ratio for read request then,

  = 0.85(0.92*10+0.08*100)+0.15(0.92*(10+100)+0.08*100)
  =31 ns

If I assume that hit ratio is 0% for write request then,

  = 0.85(0.92*10+0.08*100)+0.15(0*110+1*100)
  =29.62 ns

Upvotes: 6

Views: 55253

Answers (3)

Dimitar
Dimitar

Reputation: 4783

Your second assumption is correct.

With the write-through cache, it writes immediately the modified blocks to memory and then onto disk. Since no disk access time is given, it is eliminated from the equation. My notations are little different, but I will post it that way for future readers. I used the notation given in William Stallings Operating Systems: Internals and Design Principles.

Given: 

Tm = 100ns
Tc = 10ns /* 10x faster than Tm */ 
Hr = 0.92 /* Hit rate reading */
85% reading => 15% of the time writing

Solution:

The effective access time for reading:
Te_r = Hr * Tc + (1-Hr)Tm = 0.92*10 + (1 - 0.92)100 = 9.2 + 8 = 17.2

The effective access time for writing, is determined from the Hit rate Hw,
which is always 0, because the data must be immediately written onto the 
memory.
Te_w = Hw * Tc + (1-Hw)Tm = 0*10 + (1 - 0)100 = 100

Taking into account the percentage:
0.85*17.2 + 0.15*100 = 14.62 + 15 = 29.62

                                                                    Q.E.D

Upvotes: 3

Shubham Gupta
Shubham Gupta

Reputation: 227

Avg access time considering only read = 0.92*10 + 0.08*100 = 17.2 ns.

Avg access time considering only write = 100 ns (because in write through you have to go back to memory to update even if it is a hit or miss. if you assume hit ratio = 0.5 and miss = 0.5 then 0.5*100 + 0.5*100 = 1*100)

So, total access time for both read and write would be - 0.85*17.2 + 0.15*100 = 14.62 + 15 = 29.62 ns

**you cant assume hit ratio for write same as hit ratio for read. for write request (write through) whatever will be the case, you have to write back in the memory. so the write access time will be equal to memory access time.

Upvotes: 2

hashPJ
hashPJ

Reputation: 76

In case of write through policy and when data is directly read from main memory when cache miss occurs,

Tavg(for write)=Hw*Tm +(1-Hw)*Tm = Tm

Hw=hit ratio for write, Tm=Time to access main memory

in this formula, in both cases of cache hit & miss, we can update and read data simultaneously in Tm time itself, since usually Tm>>Tc. So Tc for reading can be ignored.

Hence you dont need to know hit ratio for write for this question. and the answer would be 29.62ns

Upvotes: 0

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