CODEWITHSUNDEEP
assemblymemorycpu-architecturecpu-cache
smrmaak
smrmaak

Reputation: 21

Computing the average memory access time with following processor and cache performance

Consider the following processor and cache configurations

Clock rate 500MHz
Base CPI 1
L1 cache type Separate Instruction and Data Cache
L1 cache write policy Write-back
L1 cache hit time 2ns
L1 miss penalty 40ns(time to read from and write to main memory)
L1 instruction cache miss rate 1%
L1 date cache miss rate 5%
dirty data cache blocks 40% of total data cache blocks

(a) Compute the average memory access time(AMAT) for Instruction cache.

(b) Compute the average memory access time(AMAT) for data cache assuming load and store represent 20% of instructions.

My answer

(a) :
According to the formula
AMAT= hit time+miss rate* miss penalty
AMAT= 2ns+0.01*40ns =2.4ns

(b) :
According to the formula
AMAT= hit time+miss rate* miss penalty
AMAT= 2ns+0.05* 40ns*0.2 =2.4ns

Above answer is my opinion but I am not sure how to use cache configurations such as dirty data cache blocks and Clock rate. Are my answers right or am I missing something? Thanks for reading!

Upvotes: 0

Views: 686

Answers (1)

Erik Eidt
Erik Eidt

Reputation: 26786

40ns(time to read from and write to main memory)

The use of the conjunction and in that text is awkward.  It could mean that 40ns = read + write-back, so 40ns for refilling a dirty cache line, but I think it is better to read that as "both" instead, so 40ns for read and also 40ns for write-back.  I would have written or there instead, to avoid the confusion between and in the sense of "both", or "as well", vs. in the sense of addition.

Your (a) looks right.

On (b):

  1. The L1 data cache suffers a miss rate of 5% and in 40% of those cases, the miss has to write-back as well as read.  So, here, we need to distinguish between the read operations and the write-back operations, since all misses incur read time, while 40% will also incur write-back time.

  2. I am not used to specifying an average access time for data (loads & stores), that includes instructions that don't access data.  However, that does make sense if at some point you want to combine the i & d-cache times to get an overall view of the AMAT per instruction.  So, going along that route, we need to apply the 20% to both hits and misses not just to misses.  I would compute the data cache performance without that 20% (i.e. given the instruction is a load or store: what is the AMAT), then factor that 20% in last to average that out over all instructions.

I don't see cycles or MHz involved in either question (a) or (b).

Upvotes: 1

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