CODEWITHSUNDEEP
vhdl
Haris Pap
Haris Pap

Reputation: 85

How to use components inside behavioral vhdl

I have created a divided with core generator. It creates a component like the following:

component divider_core
port (
clk: IN std_logic;
rfd: OUT std_logic;
dividend: IN std_logic_VECTOR(31 downto 0);
divisor: IN std_logic_VECTOR(31 downto 0);
quotient: OUT std_logic_VECTOR(31 downto 0);
fractional: OUT std_logic_VECTOR(31 downto 0));
end component;

I wonder how I could use this divider component by some behavioral vhdl code, inside a process. Is that possible?

Upvotes: 1

Views: 8428

Answers (3)

Jotorious
Jotorious

Reputation: 185

It sounds like you want to use this division_core like a function, which is probably not possible. if you want a vhdl function that implements division, that is different from using a component.

Upvotes: 0

Kshitij Agrawal
Kshitij Agrawal

Reputation: 71

Once you have created your module you need to declare the component in the architecture section and map the ports of the component before the process.

You can see how it applies to your code below

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity declaration 

architecture Behavioral of <your_entity> is

component divider_core
port (
 clk: IN std_logic;
 rfd: OUT std_logic;
 dividend: IN std_logic_VECTOR(31 downto 0);
 divisor: IN std_logic_VECTOR(31 downto 0);
 quotient: OUT std_logic_VECTOR(31 downto 0);
 fractional: OUT std_logic_VECTOR(31 downto 0));
end component;

begin

c1: divider_core Port Map (
 clk => clk,
 rfd => rfd,
 dividend => dividend,
 divisor => divisor,
 quotient => quotient,
 fractional => fractional
);

process

end process;
end Behavioral;

Upvotes: 3

simon
simon

Reputation: 1145

Include the numeric_std package (link) and use the division (/) operator.

Upvotes: 0

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